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    Viscous electropolishing system
    4.
    发明授权
    Viscous electropolishing system 失效
    粘性电解抛光系统

    公开(公告)号：US06935933B1

    公开(公告)日：2005-08-30

    申请号：US10036621

    申请日：2001-12-21

    申请人： Valeriy Sukharev ,  Wilbur G. Catabay

    发明人： Valeriy Sukharev ,  Wilbur G. Catabay

    IPC分类号： B24B7/22 ,  C25F3/02 ,  H01L21/321 ,  H01L21/768

    CPC分类号： H01L21/7684 ,  C25F3/02 ,  H01L21/32115

    摘要： A method for planarizing a surface of an electrically conductive layer on a substrate, where the surface of the electrically conductive layer has relatively high features and relatively low features. A viscous material is applied to the surface of the electrically conductive layer, whereby at least the relatively low features are covered by the viscous material. The substrate is immersed in an electrically conductive solution. An electrical potential is applied between the electrically conductive layer and an electrode within the electrically conductive solution, whereby reaction kinetics favor erosion of the electrically conductive layer. The electrically conductive solution is agitated, thereby selectively uncovering the viscous material from at least features that are relatively high, and thereby preferentially planarizing at least the features that are relatively high.

    摘要翻译： 一种用于平坦化基板上的导电层的表面的方法，其中导电层的表面具有相对较高的特征和相对较低的特征。 将粘性材料施加到导电层的表面，由此至少相对较低的特征被粘性材料覆盖。 将基板浸入导电溶液中。 在导电溶液中的导电层和电极之间施加电位，由此反应动力学有利于导电层的侵蚀。 搅动导电溶液，从而从至少相对高的特征选择性地露出粘性材料，从而优先至少平坦化至少相对高的特征。

    LOW TEMPERATURE PROCESS FOR FORMING A LOW DIELECTRIC CONSTANT FLUORINE AND CARBON-CONTAINING SILICON OXIDE DIELECTRIC-MATERIAL CHARACTERIZED BY IMPROVED RESISTANCE TO OXIDATION AND GOOD GAP-FILLING CAPABILITIES
    5.
    发明授权
    LOW TEMPERATURE PROCESS FOR FORMING A LOW DIELECTRIC CONSTANT FLUORINE AND CARBON-CONTAINING SILICON OXIDE DIELECTRIC-MATERIAL CHARACTERIZED BY IMPROVED RESISTANCE TO OXIDATION AND GOOD GAP-FILLING CAPABILITIES 有权
    用于形成低介电常数氟的低温方法和含氧化硅氧化物电介质材料，其特征在于改善了氧化和良好的填充能力

    公开(公告)号：US06365528B1

    公开(公告)日：2002-04-02

    申请号：US09590310

    申请日：2000-06-07

    申请人： Valeriy Sukharev ,  Vladimir Zubkov

    发明人： Valeriy Sukharev ,  Vladimir Zubkov

    IPC分类号： H01L2131

    CPC分类号： C23C16/401 ,  H01L21/31604 ,  H01L21/31629 ,  H01L21/31633

    摘要： A low temperature process is described for forming a low dielectric constant (k) fluorine and carbon-containing silicon oxide dielectric material for integrated circuit structures. A reactor has a semiconductor substrate mounted on a substrate support which is maintained at a low temperature not exceeding about 25° C., preferably not exceeding about 10° C., and most preferably not exceeding about 0° C. A low k fluorine and carbon-containing silicon oxide dielectric material is formed on the surface of the substrate by reacting together a vaporous source of a mild oxidizing agent, such as a vaporized hydrogen peroxide, and a vaporous substituted silane having the formula (CFmHn)—Si—(R)xHy wherein m is 1-3; n is 3-m; R is an alkyl selected from the group consisting of ethyl (—C2H5), methyl (—CH3), and mixtures thereof; x is 1-3; and y is 3-x.

    摘要翻译： 描述了用于形成用于集成电路结构的低介电常数（k）氟和含碳氧化硅电介质材料的低温工艺。 反应器具有安装在基板载体上的半导体基板，其保持在不超过约25℃，优选不超过约10℃，最优选不超过约0℃的低温。低k氟和 通过使诸如蒸发的过氧化氢之类的温和氧化剂的气态源和具有式（CFmHn）-Si（R）的气态取代的硅烷反应，在基板的表面上形成含碳氧化硅电介质材料 ）xHy，其中m为1-3; n为3-m; R是选自（-C 2 H 5），甲基（-CH 3），及其混合物的烷基的烷基; x为1-3; y为3-x。

    Method for determining via/contact pattern density effect in via/contact etch rate
    6.
    发明授权
    Method for determining via/contact pattern density effect in via/contact etch rate 有权
    确定通孔/接触蚀刻速率的通孔/接触图案密度效应的方法

    公开(公告)号：US07687303B1

    公开(公告)日：2010-03-30

    申请号：US11264930

    申请日：2005-11-01

    申请人： Valeriy Sukharev ,  Ara Markosian

    发明人： Valeriy Sukharev ,  Ara Markosian

    IPC分类号： H01L21/44

    CPC分类号： H01L21/31116 ,  H01L21/76805 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for determining an effect of via/contact pattern density in via/contact etch rate of a wafer includes determining a neutral etchant species number flux intersecting each via/contact mouth as a function of local layout characteristics and determining variations in the neutral etchant species flux number as a function of the via/contact pattern density in a wafer scale. The comparison of these number fluxes provides the capability to discriminate an underetched or an overetched via/contact from normal vias/contacts satisfying an etch tolerance criterion. Chip designers can modify the layout design to minimize via/contact failures. Chip manufacturers can modify the etching process to minimize via/contact failures.

    摘要翻译： 用于确定晶片的通孔/接触蚀刻速率中的通孔/接触图案密度的影响的方法包括确定与每个通孔/接触嘴相交的中性蚀刻剂种类数量通量作为局部布局特性的函数并确定中性蚀刻剂种类的变化 作为晶片尺度中的通孔/接触图案密度的函数的通量数。 这些数量通量的比较提供了区分未刻蚀或过蚀刻的通孔/触点与满足蚀刻耐受性标准的正常通孔/触点的能力。 芯片设计人员可以修改布局设计，以尽量减少通孔/接触故障。 芯片制造商可以修改蚀刻过程以最小化通孔/接触故障。

    Copper-low-K dual damascene interconnect with improved reliability
    7.
    发明申请
    Copper-low-K dual damascene interconnect with improved reliability 审中-公开
    铜 - 低K双镶嵌互连具有改进的可靠性

    公开(公告)号：US20050006770A1

    公开(公告)日：2005-01-13

    申请号：US10615042

    申请日：2003-07-08

    申请人： Valeriy Sukharev ,  Ratan Choudhury ,  Chong Park

    发明人： Valeriy Sukharev ,  Ratan Choudhury ,  Chong Park

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dual damascene-based interconnect structure which includes a liner of aluminum-0.5% copper alloy. The alloy can be implemented by depositing the alloy using a conventional PVD technique. To completely secure against copper atoms possibly penetrating through the aluminum-0.5% copper alloy, one or more Ta/TaN liners can be employed in addition to the aluminum-0.5% copper alloy liner. If Ta/taN is to be used, preferably the Ta/TaN is deposited before the aluminum-0.5% copper alloy is deposited.

    摘要翻译： 一种双镶嵌型互连结构，其包括铝-0.5％铜合金的衬里。 该合金可以通过使用常规PVD技术沉积合金来实现。 为了完全固定可能穿透铝-0.5％铜合金的铜原子，除了铝-0.5％的铜合金衬垫之外，还可以使用一个或多个Ta / TaN衬垫。 如果使用Ta / taN，则优选在沉积铝-0.5％铜合金之前沉积Ta / TaN。

    Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage
    9.
    发明授权
    Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage 有权
    用于处理低介电常数碳掺杂的氧化硅介电材料的暴露表面以保护材料免受损害的方法

    公开(公告)号：US06114259A

    公开(公告)日：2000-09-05

    申请号：US362645

    申请日：1999-07-27

    申请人： Valeriy Sukharev ,  Warren Uesato ,  John Rongxiang Hu ,  Wei-Jen Hsia ,  Linggian Qian

    发明人： Valeriy Sukharev ,  Warren Uesato ,  John Rongxiang Hu ,  Wei-Jen Hsia ,  Linggian Qian

    IPC分类号： H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L21/302

    CPC分类号： H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31138 ,  H01L21/31633 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

    摘要： A method for treating exposed surfaces of a low k carbon doped silicon oxide dielectric material in order to protect the low k carbon doped silicon oxide dielectric material from damage during removal of photoresist mask materials is described. The process comprises (a) first treating the exposed surfaces of a low k carbon doped silicon oxide dielectric material with a plasma capable of forming a densified layer on and adjacent the exposed surfaces of low k carbon doped silicon oxide dielectric material and (b) then treating the semiconductor wafer with a mild oxidizing agent capable of removing photoresist materials from the semiconductor wafer. These steps will prevent the degradation of the exposed surfaces of a low k carbon doped silicon oxide dielectric material during removal of an etch mask after formation of vias or contact openings in the low k carbon doped silicon oxide dielectric material.

    摘要翻译： 描述了一种用于处理低k碳掺杂的氧化硅介电材料的暴露表面以便保护低k碳掺杂的氧化硅介电材料在去除光致抗蚀剂掩模材料期间的损坏的方法。 该方法包括（a）首先用等离子体处理低k碳掺杂的氧化硅介电材料的暴露表面，所述等离子体能够在低k碳掺杂的氧化硅介电材料的暴露表面上及其附近形成致密层，并且（b）然后 用能够从半导体晶片去除光致抗蚀剂材料的温和氧化剂处理半导体晶片。 在低k碳掺杂的氧化硅电介质材料中形成通孔或接触开口之后，这些步骤将防止在去除蚀刻掩模期间低k碳掺杂的氧化硅介电材料的暴露表面的劣化。

    Method of forming variable thickness gate dielectrics
    10.
    发明授权
    Method of forming variable thickness gate dielectrics 失效
    形成可变厚度栅极电介质的方法

    公开(公告)号：US6033998A

    公开(公告)日：2000-03-07

    申请号：US38684

    申请日：1998-03-09

    申请人： Sheldon Aronowitz ,  David Chan ,  James Kimball ,  David Lee ,  John Haywood ,  Valeriy Sukharev

    发明人： Sheldon Aronowitz ,  David Chan ,  James Kimball ,  David Lee ,  John Haywood ,  Valeriy Sukharev

    IPC分类号： H01L21/8234 ,  H01L21/76

    CPC分类号： H01L21/823462

    摘要： Provided is a method of fabricating gate dielectric layers having variable thicknesses and compositions over different regions of a semiconductor wafer. In a preferred embodiment of the present invention, a gate oxide layer is first grown over the various regions. Regions that are to have a relatively thicker, unhardened gate dielectric are masked and the wafer is exposed to a remote low energy nitrogen plasma. After the nitridization process is completed, the mask is removed and the wafer is exposed to further oxidation. The regions where oxynitrides have been formed act as a barrier to the oxidation process. Consequently, different oxide thicknesses can be grown on the same wafer, thinner and hardened where nitridization has been performed, and thicker and not hardened in those regions that were masked during the nitridization. Variable thickness gate dielectrics in accordance with the present invention may be particularly advantageous in semiconductor integrated circuits involving both digital and analog devices.

    摘要翻译： 提供一种制造在半导体晶片的不同区域上具有可变厚度和组成的栅极电介质层的方法。 在本发明的优选实施例中，首先在各个区域上生长栅氧化层。 具有相对较厚，未硬化的栅极电介质的区域被掩蔽，并且晶片暴露于远程低能量氮等离子体。 在氮化处理完成之后，去除掩模并使晶片进一步氧化。 已经形成氮氧化物的区域用作氧化过程的屏障。 因此，可以在相同的晶片上生长不同的氧化物厚度，在已经进行氮化的情况下更薄并且硬化，并且在氮化期间被掩蔽的那些区域中较厚而不硬化。 根据本发明的可变厚栅极电介质在涉及数字和模拟装置的半导体集成电路中可能是特别有利的。