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    Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
    1.
    发明申请
    Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers 审中-公开
    三维CMOS集成电路具有建立在不同晶体取向晶片上的器件层

    公开(公告)号：US20050067620A1

    公开(公告)日：2005-03-31

    申请号：US10914433

    申请日：2004-08-09

    申请人： Victor Chan ,  Kathryn Guarini ,  Meikei Ieong

    发明人： Victor Chan ,  Kathryn Guarini ,  Meikei Ieong

    IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/336 ,  H01L21/68 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/00 ,  H01L27/06 ,  H01L27/085 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76 ,  H01L21/84

    CPC分类号： H01L21/6835 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2221/68368 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias. In a second 3D integration scheme, a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation is bonded to a surface of a pre-fabricating wafer having second semiconductor devices on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and forming first semiconductor device on the first SOI layer.

    摘要翻译： 提供制造3D集成电路的三维（3D）积分方案，其中pFET位于该器件的最佳晶体表面上，并且nFET位于用于该类型器件的最佳晶体表面上。 根据本发明的第一3D集成方案，第一半导体器件预先构建在第一绝缘体上硅（SOI）衬底的半导体表面上，并且第二半导体器件预先构建在第一绝缘体上硅绝缘体 第二SOI衬底。 在预先构建这两个结构之后，将结构粘合在一起并通过晶片通孔通孔进行互连。 在第二3D集成方案中，具有第一晶体取向的第一SOI层的绝缘硅绝缘体（SOI）衬底被结合到具有第二SOI层的具有第二半导体器件的预制晶片的表面上，所述第二SOI层具有 不同于第一SOI层的晶体取向; 以及在所述第一SOI层上形成第一半导体器件。

    Integration of strained Ge into advanced CMOS technology
    2.
    发明申请
    Integration of strained Ge into advanced CMOS technology 失效
    将应变锗融入先进的CMOS技术

    公开(公告)号：US20050285097A1

    公开(公告)日：2005-12-29

    申请号：US10876155

    申请日：2004-06-24

    申请人： Huiling Shang ,  Meikei Ieong ,  Jack Chu ,  Kathryn Guarini

    发明人： Huiling Shang ,  Meikei Ieong ,  Jack Chu ,  Kathryn Guarini

    IPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/7841

    摘要： A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

    摘要翻译： 公开了一种用于压缩应变Ge层中的PFET器件的结构和方法。 这种器件的制造方法与标准CMOS技术兼容，并且具有完全可扩展性。 该处理包括超过50％Ge含量缓冲层，纯Ge层和SiGe顶层的选择性外延沉积。 承载在压缩应变Ge层中的制造掩埋沟道PMOS器件相对于类似的Si器件显示出优异的器件特性。

    Self-aligned SOI with different crystal orientation using WAFER bonding and SIMOX processes
    3.
    发明申请
    Self-aligned SOI with different crystal orientation using WAFER bonding and SIMOX processes 失效
    使用WAFER键合和SIMOX工艺，具有不同晶体取向的自对准SOI

    公开(公告)号：US20050070077A1

    公开(公告)日：2005-03-31

    申请号：US10967398

    申请日：2004-10-18

    申请人： Kathryn Guarini ,  Meikei Ieong ,  Leathen Shi ,  Min Yang

    发明人： Kathryn Guarini ,  Meikei Ieong ,  Leathen Shi ,  Min Yang

    IPC分类号： H01L27/12 ,  H01L21/335 ,  H01L21/762 ,  H01L27/08 ,  H01L29/04

    CPC分类号： H01L21/76275 ,  H01L21/76267 ,  H01L21/76283

    摘要： The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.

    摘要翻译： 本发明提供了在具有不同晶体取向的SOI衬底上形成的集成半导体器件，其为特定器件提供最佳性能。 具体地说，一种集成半导体结构，其至少包括具有第一晶体取向的顶部半导体层和第二晶体取向的半导体材料的SOI衬底，其中半导体材料基本上是共面的，并且具有与顶部基本相同的厚度 半导体层和第一晶体取向与第二晶体取向不同。 SOI衬底通过晶片接合，离子注入和退火形成。

    Self-aligned planar double-gate process by self-aligned oxidation
    4.
    发明申请
    Self-aligned planar double-gate process by self-aligned oxidation 有权
    自对准平面双栅极工艺通过自对准氧化

    公开(公告)号：US20050059252A1

    公开(公告)日：2005-03-17

    申请号：US10663471

    申请日：2003-09-15

    申请人： Omer Dokumaci ,  Bruce Doris ,  Kathryn Guarini ,  Suryanarayan Hegde ,  MeiKei Ieong ,  Erin Jones

    发明人： Omer Dokumaci ,  Bruce Doris ,  Kathryn Guarini ,  Suryanarayan Hegde ,  MeiKei Ieong ,  Erin Jones

    IPC分类号： H01L20060101 ,  H01L21/033 ,  H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L29/423 ,  H01L29/786

    CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

    摘要： A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

    摘要翻译： 双栅极晶体管具有通过在前栅极附近形成对称侧壁然后在至少1000度的温度下氧化背栅电极足以缓解应力的时间的方法横向排列的前（上）和后门 在该结构中，氧化物从晶体管主体的侧面渗透，以增厚外边缘上的背栅氧化层，留下中心的栅极氧化物的有效厚度，与前栅电极对准。 任选地，来自氧化物增强物质的侧面的成角度的植入物鼓励外部注入区域中相对较厚的氧化物，并且跨越晶体管体的氧化物延迟植入阻碍垂直方向上的氧化，从而允许增加氧化的横向范围。

    HIGH-PERFORMANCE CMOS SOI DEVICES ON HYBRID CRYSTAL-ORIENTED SUBSTRATES
    5.
    发明申请
    HIGH-PERFORMANCE CMOS SOI DEVICES ON HYBRID CRYSTAL-ORIENTED SUBSTRATES 失效
    高性能CMOS SOI器件在混合晶体导向衬底上的应用

    公开(公告)号：US20080096330A1

    公开(公告)日：2008-04-24

    申请号：US11958877

    申请日：2007-12-18

    申请人： Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey Sleight ,  Min Yang

    发明人： Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Kern Rim ,  Jeffrey Sleight ,  Min Yang

    IPC分类号： H01L21/84

    CPC分类号： H01L21/76275 ,  H01L21/823807 ,  H01L21/84

    摘要： An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.

    摘要翻译： 提供包含至少一个器件的集成半导体结构，所述器件形成在对于该器件最佳的第一晶体表面上，而另一器件形成在对于另一器件最佳的第二不同晶体表面上。 形成集成结构的方法包括提供包括至少第一晶体取向的第一半导体层和第二不同晶体取向的第二半导体层的键合衬底。 键合衬底的一部分被保护以限定第一器件区域，而键合衬底的另一部分是未受保护的。 然后蚀刻键合衬底的未保护部分以暴露第二半导体层的表面，并将半导体材料重新生长在暴露表面上。 在平坦化之后，在第一器件区域中形成第一半导体器件，并且在再生长材料上形成第二半导体器件。

    SELF-ALIGNED PLANAR DOUBLE-GATE PROCESS BY SELF-ALIGNED OXIDATION
    7.
    发明申请
    SELF-ALIGNED PLANAR DOUBLE-GATE PROCESS BY SELF-ALIGNED OXIDATION 有权
    自对准氧化自对准平面双门过程

    公开(公告)号：US20070138556A1

    公开(公告)日：2007-06-21

    申请号：US11676030

    申请日：2007-02-16

    申请人： Omer Dokumaci ,  Bruce Doris ,  Kathryn Guarini ,  Suryanarayan Hegde ,  Meikei Ieong ,  Erin Jones

    发明人： Omer Dokumaci ,  Bruce Doris ,  Kathryn Guarini ,  Suryanarayan Hegde ,  Meikei Ieong ,  Erin Jones

    IPC分类号： H01L27/12

    CPC分类号： H01L29/78648 ,  H01L21/0338 ,  H01L21/2007 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42384

    摘要： A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

    摘要翻译： 双栅极晶体管具有通过在前栅极附近形成对称侧壁然后在至少1000度的温度下氧化背栅电极足以缓解应力的时间的方法横向排列的前（上）和后门 在该结构中，氧化物从晶体管主体的侧面渗透，以增厚外边缘上的背栅氧化层，留下中心的栅极氧化物的有效厚度，与前栅电极对准。 任选地，来自氧化物增强物质的侧面的成角度的植入物鼓励外部注入区域中相对较厚的氧化物，并且跨越晶体管体的氧化物延迟植入阻碍垂直方向上的氧化，从而允许增加氧化的横向范围。