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    TEST STRUCTURE AND METHOD FOR DETECTING VIA CONTACT SHORTING IN SHALLOW TRENCH ISOLATION REGIONS
    3.
    发明申请
    TEST STRUCTURE AND METHOD FOR DETECTING VIA CONTACT SHORTING IN SHALLOW TRENCH ISOLATION REGIONS 有权
    通过短路分离区域接触短路检测的测试结构和方法

    公开(公告)号：US20080057667A1

    公开(公告)日：2008-03-06

    申请号：US11469940

    申请日：2006-09-05

    申请人： Huilong Zhu ,  Shih-Fen Huang ,  Effendi Leobandung

    发明人： Huilong Zhu ,  Shih-Fen Huang ,  Effendi Leobandung

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76227 ,  H01L21/823481 ,  H01L22/34

    摘要： A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.

    摘要翻译： 用于检测半导体器件层中的空隙形成的测试结构包括形成在衬底中的多个有源器件区域，分离有源器件区域的多个浅沟槽隔离（STI）区域，跨过有源器件形成的多个栅电极结构 区域和STI区域，以及形成在有源器件区域上和栅电极结构之间的通孔矩阵。 给定一个STI区域的相对端处的一对通孔中的每一个的至少一个边缘至少延伸到相关联的有源器件区域的边缘。

    Structure and method to improve SRAM stability without increasing cell area or off current
    4.
    发明授权
    Structure and method to improve SRAM stability without increasing cell area or off current 失效
    提高SRAM稳定性的结构和方法，不增加单元面积或关断电流

    公开(公告)号：US06984564B1

    公开(公告)日：2006-01-10

    申请号：US10710184

    申请日：2004-06-24

    申请人： Shih-Fen Huang ,  Clement Wann ,  Haining S. Yang

    发明人： Shih-Fen Huang ,  Clement Wann ,  Haining S. Yang

    IPC分类号： H01L21/8234 ,  H01L21/8238

    CPC分类号： H01L29/7842 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7843

    摘要： An SRAM in a CMOS integrated circuit is subjected to stress on the channels of its transistors; compressive stress on the pull-up and pass gate transistors and tensile stress on the pull-down transistors in a version designed to improve stability; and compressive stress on the pull-up transistors and tensile stress on the pull-down and pass gate transistors in a version designed to reduce the cell size and increase speed of operation.

    摘要翻译： CMOS集成电路中的SRAM在其晶体管的沟道上受到应力; 上拉和栅极晶体管中的压应力和下拉晶体管中的拉伸应力，旨在提高稳定性; 并且上拉晶体管中的压应力和下拉和通过栅极晶体管中的拉伸应力在设计成减小电池尺寸并增加操作速度的版本中。

    Test structure for detecting via contact shorting in shallow trench isolation regions
    5.
    发明授权
    Test structure for detecting via contact shorting in shallow trench isolation regions 有权
    用于检测浅沟槽隔离区域中接触短路的测试结构

    公开(公告)号：US08138497B2

    公开(公告)日：2012-03-20

    申请号：US12140479

    申请日：2008-06-17

    申请人： Huilong Zhu ,  Shih-Fen Huang ,  Effendi Leobandung

    发明人： Huilong Zhu ,  Shih-Fen Huang ,  Effendi Leobandung

    IPC分类号： H01L23/544

    CPC分类号： H01L21/76227 ,  H01L21/823481 ,  H01L22/34

    摘要： A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.

    摘要翻译： 用于检测半导体器件层中的空隙形成的测试结构包括形成在衬底中的多个有源器件区域，分离有源器件区域的多个浅沟槽隔离（STI）区域，跨过有源器件形成的多个栅电极结构 区域和STI区域，以及形成在有源器件区域上和栅电极结构之间的通孔矩阵。 给定一个STI区域的相对端处的一对通孔中的每一个的至少一个边缘至少延伸到相关联的有源器件区域的边缘。

    Low-cost FEOL for ultra-low power, near sub-vth device structures
    6.
    发明授权
    Low-cost FEOL for ultra-low power, near sub-vth device structures 有权
    低成本的FEOL用于超低功耗，靠近次级装置结构

    公开(公告)号：US07816738B2

    公开(公告)日：2010-10-19

    申请号：US11164651

    申请日：2005-11-30

    申请人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Jeffrey P. Gambino ,  Shih-Fen Huang ,  Edward J. Nowak ,  Anthony K. Stamper

    发明人： Brent A. Anderson ,  Andres Bryant ,  William F. Clark, Jr. ,  Jeffrey P. Gambino ,  Shih-Fen Huang ,  Edward J. Nowak ,  Anthony K. Stamper

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

    摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.

    摘要翻译： 为了降低功耗要求，获得全电位晶体管性能，并避免在高密度集成电路中对晶体管性能的功耗限制，晶体管工作在亚阈值（sub-Vth）或接近sub-Vth电压方式 约0.2伏，而不是约1.2伏特或更高的超电压状态），并且为了这种操作而进行了优化，特别是通过简化晶体管结构，因为在Vth的工作电压方案中固有的沟道电阻是主要的。 这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构 简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

    TEST STRUCTURE FOR DETECTING VIA CONTACT SHORTING IN SHALLOW TRENCH ISOLATION REGIONS
    7.
    发明申请
    TEST STRUCTURE FOR DETECTING VIA CONTACT SHORTING IN SHALLOW TRENCH ISOLATION REGIONS 有权
    用于通过SHOREOW TRENCH隔离区域中的接触短路检测的测试结构

    公开(公告)号：US20080246032A1

    公开(公告)日：2008-10-09

    申请号：US12140479

    申请日：2008-06-17

    申请人： Huilong Zhu ,  Shih-Fen Huang ,  Effendi Leobandung

    发明人： Huilong Zhu ,  Shih-Fen Huang ,  Effendi Leobandung

    IPC分类号： H01L21/66

    CPC分类号： H01L21/76227 ,  H01L21/823481 ,  H01L22/34

    摘要： A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.

    摘要翻译： 用于检测半导体器件层中的空隙形成的测试结构包括形成在衬底中的多个有源器件区域，分离有源器件区域的多个浅沟槽隔离（STI）区域，跨过有源器件形成的多个栅电极结构 区域和STI区域，以及形成在有源器件区域上和栅电极结构之间的通孔矩阵。 给定一个STI区域的相对端处的一对通孔中的每一个的至少一个边缘至少延伸到相关联的有源器件区域的边缘。

    Test structure and method for detecting via contact shorting in shallow trench isolation regions
    8.
    发明授权
    Test structure and method for detecting via contact shorting in shallow trench isolation regions 有权
    在浅沟槽隔离区域通过接触短路检测的测试结构和方法

    公开(公告)号：US07416986B2

    公开(公告)日：2008-08-26

    申请号：US11469940

    申请日：2006-09-05

    申请人： Huilong Zhu ,  Shih-Fen Huang ,  Effendi Leobandung

    发明人： Huilong Zhu ,  Shih-Fen Huang ,  Effendi Leobandung

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76227 ,  H01L21/823481 ,  H01L22/34

    摘要： A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode structures formed across the active device areas and the STI regions, and a matrix of vias formed over the active device areas and between the gate electrode structures. At least one edge of each of a pair of vias at opposite ends of a given one of the STI regions extends at least out to an edge of the associated active device area.

    摘要翻译： 用于检测半导体器件层中的空隙形成的测试结构包括形成在衬底中的多个有源器件区域，分离有源器件区域的多个浅沟槽隔离（STI）区域，跨过有源器件形成的多个栅电极结构 区域和STI区域，以及形成在有源器件区域上和栅电极结构之间的通孔矩阵。 给定一个STI区域的相对端处的一对通孔中的每一个的至少一个边缘至少延伸到相关联的有源器件区域的边缘。

    Method of fabricating an indium field implant for punchthrough protection in semiconductor devices
    10.
    发明授权
    Method of fabricating an indium field implant for punchthrough protection in semiconductor devices 有权
    制造用于半导体器件中穿透保护的铟场植入物的方法

    公开(公告)号：US06342429B1

    公开(公告)日：2002-01-29

    申请号：US09469579

    申请日：1999-12-22

    申请人： Helmut Puchner ,  Shih-Fen Huang

    发明人： Helmut Puchner ,  Shih-Fen Huang

    IPC分类号： H01L2176

    CPC分类号： H01L21/8238 ,  H01L21/76237

    摘要： Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is an order of magnitude smaller than that of boron and the activation level of indium is high enough for well dopings. Thus, the implanted indium is able to keep the concentration of p-dopant at the p-n well junction under the field isolation and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.

    摘要翻译： 提供了一种用于在STI沟槽底部形成铟场注入的技术，以加强场氧化物下的p阱，但不会削弱场氧化物下的n阱。 铟的扩散系数比硼的扩散系数小一个数量级，铟的激活电位足够高以使阱掺杂。 因此，即使在硼耗尽的情况下，注入的铟能够在场隔离下保持p-n阱结的p型掺杂浓度，并且氧化物/硅界面也能保持高浓度，从而避免穿透。