公开(公告)号：US07317630B2

公开(公告)日：2008-01-08

申请号：US11182374

申请日：2005-07-15

申请人： Nicola Telecco ,  Vijay P. Adusumilli ,  Anil Gupta ,  Edward Hui ,  Steven J. Schumann

发明人： Nicola Telecco ,  Vijay P. Adusumilli ,  Anil Gupta ,  Edward Hui ,  Steven J. Schumann

IPC分类号： G11C5/06

CPC分类号： G11C7/10 ,  H01L2224/05553 ,  H01L2224/48137 ,  H01L2224/49175

摘要： A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.

摘要翻译： 非易失性存储装置包括单独的控制器电路和存储器电路。 控制器电路制造在第一集成电路芯片上。 控制器电路包括多个电荷泵电路，系统接口逻辑电路，存储器控制逻辑电路和一个或多个模拟电路。 存储器电路制造在第二集成电路芯片上，并且包括列解码器，行解码器，控制寄存器和数据寄存器。 存储器控制器接口区域包括第一集成电路芯片上的第一多个管芯接合焊盘和第二集成电路芯片上的第二多个管芯接合焊盘，使得第一和第二集成电路芯片可以芯片结合在一起。 单个控制器电路可以与多个存储器电路接口，从而进一步降低总体成本，因为每个存储器电路不需要专用控制器电路。

公开(公告)号：US07633800B2

公开(公告)日：2009-12-15

申请号：US11835572

申请日：2007-08-08

申请人： Vijay P. Adusumilli ,  Nicola Telecco

发明人： Vijay P. Adusumilli ,  Nicola Telecco

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C29/846

摘要： Column redundancy is provided outside of a FLASH memory chip using a separate companion controller chip. The companion chip initially receives and stores fuse address information from the FLASH memory chip for defective memory cells in the FLASH memory. In a read mode of operation, the companion control chip detects receipt of a defective address from the FLASH memory and stores in a redundant shift register redundant data that is downloaded from the FLASH memory chip. The redundant data is used to provide correct FLASH memory data to an external user that interfaces with the companion control chip. In a program mode of operation, the companion control chip provides redundant bits that are stored in redundant columns in the FLASH memory chip. The companion control chip provides flexibility by readily providing a number of different redundancy schemes for bits, nibbles, or bytes without requiring additional logic circuits in the FLASH memory chip itself. Data is transferred between the FLASH memory chip and the companion control chip a byte at a time.

摘要翻译： 使用单独的伴随控制器芯片在闪存芯片的外部提供列冗余。 伴随芯片最初接收并存储来自FLASH存储器芯片的熔丝地址信息用于闪速存储器中的有缺陷的存储单元。 在读取操作模式中，伴随控制芯片检测从FLASH存储器接收到缺陷地址，并存储在从闪速存储器芯片下载的冗余移位寄存器冗余数据中。 冗余数据用于向与配套控制芯片接口的外部用户提供正确的FLASH存储器数据。 在程序操作模式中，伴随控制芯片提供存储在闪速存储器芯片中的冗余列中的冗余位。 伴随的控制芯片通过容易地为位，半字节或字节提供多种不同的冗余方案来提供灵活性，而不需要FLASH存储器芯片本身中的附加逻辑电路。 数据在闪存存储器芯片和伴随控制芯片之间一个字节一次传输。

公开(公告)号：US20090040825A1

公开(公告)日：2009-02-12

申请号：US11835572

申请日：2007-08-08

申请人： Vijay P. Adusumilli ,  Nicola Telecco

发明人： Vijay P. Adusumilli ,  Nicola Telecco

IPC分类号： G11C29/24

CPC分类号： G11C29/846

摘要： Column redundancy is provided outside of a FLASH memory chip using a separate companion controller chip. The companion chip initially receives and stores fuse address information from the FLASH memory chip for defective memory cells in the FLASH memory. In a read mode of operation, the companion control chip detects receipt of a defective address from the FLASH memory and stores in a redundant shift register redundant data that is downloaded from the FLASH memory chip. The redundant data is used to provide correct FLASH memory data to an external user that interfaces with the companion control chip. In a program mode of operation, the companion control chip provides redundant bits that are stored in redundant columns in the FLASH memory chip. The companion control chip provides flexibility by readily providing a number of different redundancy schemes for bits, nibbles, or bytes without requiring additional logic circuits in the FLASH memory chip itself. Data is transferred between the FLASH memory chip and the companion control chip a byte at a time.

摘要翻译： 使用单独的伴随控制器芯片在闪存芯片的外部提供列冗余。 伴随芯片最初接收并存储来自FLASH存储器芯片的熔丝地址信息用于闪速存储器中的有缺陷的存储单元。 在读取操作模式中，伴随控制芯片检测从FLASH存储器接收到缺陷地址，并存储在从闪速存储器芯片下载的冗余移位寄存器冗余数据中。 冗余数据用于向与配套控制芯片接口的外部用户提供正确的FLASH存储器数据。 在程序操作模式中，伴随控制芯片提供存储在闪速存储器芯片中的冗余列中的冗余位。 伴随的控制芯片通过容易地为位，半字节或字节提供多种不同的冗余方案来提供灵活性，而不需要FLASH存储器芯片本身中的附加逻辑电路。 数据在闪存存储器芯片和伴随控制芯片之间一个字节一次传输。

公开(公告)号：US07971024B2

公开(公告)日：2011-06-28

申请号：US12351707

申请日：2009-01-09

申请人： Vijay P. Adusumilli

发明人： Vijay P. Adusumilli

IPC分类号： G06F12/08

CPC分类号： G06F13/1668

摘要： A communication interface, coupling a controller device to one or more memory devices, provides a high-voltage reset interface. The high-voltage reset interface provides a high-voltage signal to reset the one or more memory devices. The high-voltage reset interface is implemented using a single interconnect line. The reset voltage signal is greater than a maximum voltage representing a high logic value. The communication interface may also include a bi-directional data and address interface that is used to send address, data, and commands between the controller device and the one or more memory devices. A method of transferring information between the controller device and the one or more non-volatile memory devices includes resetting the one or more non-volatile memory devices by asserting a high-voltage signal on the high-voltage reset interface and sending a command from the controller device to the one or more non-volatile memory devices via the data and address interface.

摘要翻译： 将控制器设备耦合到一个或多个存储器设备的通信接口提供高电压复位接口。 高电压复位接口提供高电压信号来复位一个或多个存储器件。 高电压复位接口使用单个互连线实现。 复位电压信号大于表示高逻辑值的最大电压。 通信接口还可以包括用于在控制器设备和一个或多个存储器设备之间发送地址，数据和命令的双向数据和地址接口。 一种在控制器设备和一个或多个非易失性存储器件之间传送信息的方法包括通过在高电压复位接口上断言高电压信号来复位一个或多个非易失性存储器件，并从 控制器设备经由数据和地址接口连接到一个或多个非易失性存储器设备。

公开(公告)号：US20090287896A1

公开(公告)日：2009-11-19

申请号：US12351707

申请日：2009-01-09

申请人： Vijay P. Adusumilli

发明人： Vijay P. Adusumilli

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F13/1668

摘要： A communication interface, coupling a controller device to one or more memory devices, provides a high-voltage reset interface. The high-voltage reset interface provides a high-voltage signal to reset the one or more memory devices. The high-voltage reset interface is implemented using a single interconnect line. The reset voltage signal is greater than a maximum voltage representing a high logic value. The communication interface may also include a bi-directional data and address interface that is used to send address, data, and commands between the controller device and the one or more memory devices. A method of transferring information between the controller device and the one or more non-volatile memory devices includes resetting the one or more non-volatile memory devices by asserting a high-voltage signal on the high-voltage reset interface and sending a command from the controller device to the one or more non-volatile memory devices via the data and address interface.

摘要翻译： 将控制器设备耦合到一个或多个存储器设备的通信接口提供高电压复位接口。 高电压复位接口提供高电压信号来复位一个或多个存储器件。 高电压复位接口使用单个互连线实现。 复位电压信号大于表示高逻辑值的最大电压。 通信接口还可以包括用于在控制器设备和一个或多个存储器设备之间发送地址，数据和命令的双向数据和地址接口。 一种在控制器设备和一个或多个非易失性存储器件之间传送信息的方法包括通过在高电压复位接口上断言高电压信号来复位一个或多个非易失性存储器件，并从 控制器设备经由数据和地址接口连接到一个或多个非易失性存储器设备。

公开(公告)号：US07515469B1

公开(公告)日：2009-04-07

申请号：US11862436

申请日：2007-09-27

申请人： Alan Chen ,  Neville Ichhaporia ,  Vijay P. Adusumilli ,  Stephen Trinh

发明人： Alan Chen ,  Neville Ichhaporia ,  Vijay P. Adusumilli ,  Stephen Trinh

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C29/848 ,  G11C16/04 ,  G11C29/789 ,  G11C2229/726

摘要： A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip.

摘要翻译： 用于非易失性存储器的列冗余系统包括单独的伴随控制器芯片，其包括用于存储有缺陷的非易失性存储器单元的地址的列冗余RAM存储器阵列。 列冗余匹配逻辑提供对应于非易失性存储器的特定用户输入地址与有缺陷的非易失性存储器单元的地址的匹配的匹配输出信号，存储在列冗余RAM存储器阵列中的所述地址的收集 。 列冗余替换逻辑响应于匹配输出，动态地将与有缺陷的非易失性存储器单元相关联的正确数据替换为非易失性存储器芯片的I / O程序或读取数据位流。

公开(公告)号：US07478213B2

公开(公告)日：2009-01-13

申请号：US11393549

申请日：2006-03-29

申请人： Vijay P. Adusumilli

发明人： Vijay P. Adusumilli

IPC分类号： G06F12/00

CPC分类号： G06F13/1668

摘要： A communication interface, coupling a controller device to one or more memory devices, provides a high-voltage reset interface. The high-voltage reset interface provides a high-voltage signal to reset the one or more memory devices. The high-voltage reset interface is implemented using a single interconnect line. The reset voltage signal is greater than a maximum voltage representing a high logic value. The communication interface may also include a bi-directional data and address interface that is used to send address, data, and commands between the controller device and the one or more memory devices. A method of transferring information between the controller device and the one or more non-volatile memory devices includes resetting the one or more non-volatile memory devices by asserting a high-voltage signal on the high-voltage reset interface and sending a command from the controller device to the one or more non-volatile memory devices via the data and address interface.

摘要翻译： 将控制器设备耦合到一个或多个存储器设备的通信接口提供高电压复位接口。 高电压复位接口提供高电压信号来复位一个或多个存储器件。 高电压复位接口使用单个互连线实现。 复位电压信号大于表示高逻辑值的最大电压。 通信接口还可以包括用于在控制器设备和一个或多个存储器设备之间发送地址，数据和命令的双向数据和地址接口。 一种在控制器设备和一个或多个非易失性存储器件之间传送信息的方法包括通过在高电压复位接口上断言高电压信号来复位一个或多个非易失性存储器件，并从 控制器设备经由数据和地址接口连接到一个或多个非易失性存储器设备。

公开(公告)号：US07640398B2

公开(公告)日：2009-12-29

申请号：US11178713

申请日：2005-07-11

申请人： Vijay P. Adusumilli

发明人： Vijay P. Adusumilli

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/0897 ,  G06F2212/2022 ,  G11C7/1039 ,  G11C16/26 ,  G11C2207/2245

摘要： A memory circuit and a method of operating a flash or EEPROM device that has two levels of internal cache. A memory device having a memory array, sense amplifiers, a data register, cache, an input-output circuit, and a control logic circuit is configured to output data while simultaneously reading data from the memory array to the data register or simultaneously copying data from the data register to a first level of internal cache. In addition, the memory device is configured to output data while simultaneously writing data from the data register to the memory array.

摘要翻译： 存储器电路和操作具有两级内部高速缓存的闪存或EEPROM器件的方法。 具有存储器阵列，读出放大器，数据寄存器，高速缓存，输入输出电路和控制逻辑电路的存储器件被配置为输出数据，同时将数据从存储器阵列读取到数据寄存器，或者同时从 数据寄存器到第一级内部缓存。 此外，存储器件被配置为输出数据，同时将数据从数据寄存器写入存储器阵列。

公开(公告)号：US20090086541A1

公开(公告)日：2009-04-02

申请号：US11862436

申请日：2007-09-27

申请人： Alan Chen ,  Neville Ichhaporia ,  Vijay P. Adusumilli ,  Stephen Trinh

发明人： Alan Chen ,  Neville Ichhaporia ,  Vijay P. Adusumilli ,  Stephen Trinh

IPC分类号： G11C16/06

CPC分类号： G11C29/848 ,  G11C16/04 ,  G11C29/789 ,  G11C2229/726

摘要： A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip.

摘要翻译： 用于非易失性存储器的列冗余系统包括单独的伴随控制器芯片，其包括用于存储有缺陷的非易失性存储器单元的地址的列冗余RAM存储器阵列。 列冗余匹配逻辑提供对应于非易失性存储器的特定用户输入地址与有缺陷的非易失性存储器单元的地址的匹配的匹配输出信号，存储在列冗余RAM存储器阵列中的所述地址的收集 。 列冗余替换逻辑响应于匹配输出，动态地将与有缺陷的非易失性存储器单元相关联的正确数据替换为非易失性存储器芯片的I / O程序或读取数据位流。