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    Method for making the self-aligned gate contact of a semiconductor device
    4.
    发明授权
    Method for making the self-aligned gate contact of a semiconductor device 失效
    用于制造半导体器件的自对准栅极接触的方法

    公开(公告)号：US3866310A

    公开(公告)日：1975-02-18

    申请号：US39531973

    申请日：1973-09-07

    Applicant: WESTINGHOUSE ELECTRIC CORP

    Inventor： DRIVER MICHAEL C ,  GEISLER MARTIN J

    IPC: H01L29/80 ,  H01L21/00 ,  H01L21/338 ,  H01L29/00 ,  H01L29/47 ,  H01L29/812 ,  H01L29/872 ,  B01J17/00

    CPC classification number: H01L29/00 ,  H01L21/00 ,  H01L29/812

    Abstract: A self-aligned gate contact of a semiconductor device is made without etching the semiconductor member during the gate contact forming step. A metal layer for forming contacts of the semiconductor device is deposited on a major surface of the semiconductor member and thereafter overlaid with a resist layer. A window pattern corresponding to the desired gate contact is formed in the resist layer, and the metal layer is undercut and removed adjacent the window pattern to expose portions of the major surface of the semiconductor member and to form overhanging portions of the resist layer adjacent the window pattern. Simultaneously with the undercutting, at least portions of contacts of the semiconductor device are formed in the metal layer. The desired gate contact is then self-aligned on the major surface by deposition through the window pattern in the resist layer. The method is particularly useful in making Schottky barrier gate field-effect transistors with high frequency capability, which requires minimal distance between source and drain contacts with an electrically separate Schottky barrier gate contact therebetween.

    Abstract translation: 在栅极接触形成步骤期间，半导体器件的自对准栅极接触被制成而不蚀刻半导体部件。 用于形成半导体器件的接触的金属层沉积在半导体部件的主表面上，然后用抗蚀剂层覆盖。 在抗蚀剂层中形成与所需的栅极接触相对应的窗口图案，并且金属层与窗口图案相邻地被切削和去除，以暴露半导体部件的主表面的部分，并形成邻近的抗蚀剂层的悬垂部分 窗口图案 与底切同时，在金属层中形成半导体器件的至少一部分触点。 然后通过沉积穿过抗蚀剂层中的窗口图案，使主要表面上所需的栅极接触自对准。 该方法在制造具有高频能力的肖特基势垒栅极场效应晶体管中是特别有用的，其需要在源极和漏极接触之间的最小距离与它们之间的电隔离的肖特基势垒栅极接触。

    Self-aligned gate field effect transistor and method of preparing
    5.
    发明授权
    Self-aligned gate field effect transistor and method of preparing 失效
    自对准门控场效应晶体管及其制备方法

    公开(公告)号：US3678573A

    公开(公告)日：1972-07-25

    申请号：US3678573D

    申请日：1970-03-10

    Applicant: WESTINGHOUSE ELECTRIC CORP

    Inventor： DRIVER MICHAEL C

    IPC: H01L23/485 ,  H01L29/00 ,  B01J17/00 ,  H01G13/00

    CPC classification number: H01L23/485 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S148/051 ,  Y10S148/139 ,  Y10S148/143 ,  H01L2924/00

    Abstract: This disclosure relates to a high frequency field effect transistor with and accurately aligned gate contact disposed between source and drain contacts. The device consists of a substrate having a substantially flat upper surface, a layer of lightly doped semiconductor material having its bottom surface disposed on the surface of the substrate and a metal layer disposed on the upper surface of the layer of semiconductor material. An aperture is formed through the metal layer into the layer of semiconductor material. The gate contact is disposed within the aperture while the metal layer around the periphery of the aperture form the source and drain contacts.

    Abstract translation: 本公开涉及一种具有设置在源极和漏极触点之间并具有精确对准的栅极接触的高频场效应晶体管。 该器件由具有基本上平坦的上表面的衬底，具有设置在衬底的表面上的其底表面的轻掺杂半导体材料层和设置在该半导体材料层的上表面上的金属层组成。 通过金属层形成半导体材料层的孔。 栅极触点设置在孔内，而围绕孔的周边的金属层形成源极和漏极接触。

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