公开(公告)号：US20110304031A1

公开(公告)日：2011-12-15

申请号：US13157491

申请日：2011-06-10

申请人： Teiji SHINDO ,  Shinji Ota

发明人： Teiji SHINDO ,  Shinji Ota

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/60 ,  H01L23/3107 ,  H01L23/3192 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/04 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49173 ,  H01L2224/49175 ,  H01L2224/78313 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/859 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1424 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00012

摘要： Disclosed is a semiconductor device including a printed-circuit board which includes a plurality of first electrodes, a plurality of second electrodes and a semiconductor chip on which a plurality of first connection pads are aligned in a first line being disposed along an outer circumference side of a top surface and a plurality of second connection pads are aligned in a second line being disposed inside of and apart from the first line, when the semiconductor chip is seen from above, and any of the plurality of first connection pads are used for a power voltage terminal and a system reset terminal of the semiconductor device.

摘要翻译： 公开了一种半导体器件，其包括印刷电路板，该印刷电路板包括多个第一电极，多个第二电极和半导体芯片，多个第一连接焊盘沿着第一线的外周侧沿第一线排列， 当从上方观察半导体芯片时，顶表面和多个第二连接焊盘在第二线中排列，第二线设置在第一线的内部并与第一线分离，并且多个第一连接焊盘中的任一个用于功率 电压端子和半导体器件的系统复位端子。

公开(公告)号：US20240332137A1

公开(公告)日：2024-10-03

申请号：US18741266

申请日：2024-06-12

申请人： ROHM CO., LTD.

发明人： Ryohei UMENO ,  Hiroaki MATSUBARA

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/49541 ,  H01L25/0655 ,  H01L24/48 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2924/1424 ,  H01L2924/182

摘要： An electronic device includes an electronic component, a sealing resin covering the electronic component, first and second terminals protruding from the sealing resin toward a first side in a first direction, and plural third terminals protruding from the sealing resin toward a second side in the first direction. The first and second terminals are located side by side with a first interval in a second direction. The third terminals are arranged in the second direction with a second interval. The first interval is greater than the second interval. Along the second direction, the first mount portion of the first terminal has a first dimension, the second mount portion of the second terminal has a second dimension, and the third mount portion of each third terminal has a third dimension. The first and second dimensions are greater than the third dimension.

公开(公告)号：US09607949B2

公开(公告)日：2017-03-28

申请号：US14641864

申请日：2015-03-09

申请人： Kabushiki Kaisha Toshiba

发明人： Hiroshi Yamada

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/04 ,  H01L23/00 ,  H01L23/29 ,  H01L23/433 ,  H01L23/36 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L23/5386 ,  H01L21/568 ,  H01L23/295 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/1424 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/11

摘要： A semiconductor device includes a first semiconductor unit including a plurality of first semiconductor chips, an organic resin provided between the first semiconductor chips, a wiring layer provided above the first semiconductor chips to electrically connect the first semiconductor chips to each other, and a plurality of connecting terminals provided on an upper portion of the wiring layer and a second semiconductor unit fixed to a wiring layer side of the first semiconductor unit, the second semiconductor unit fixed to a region sandwiched between the connecting terminals, the second semiconductor unit having a second semiconductor chip, the second semiconductor unit electrically connected to the first semiconductor unit.

公开(公告)号：US11862631B2

公开(公告)日：2024-01-02

申请号：US16937061

申请日：2020-07-23

申请人： Hitachi, Ltd.

发明人： Ryo Kuwana ,  Masahiro Masunaga ,  Mutsumi Suzuki ,  Isao Hara

IPC分类号： H01L27/088 ,  G01L9/00 ,  G21C17/00 ,  H01L23/498 ,  H01L23/00 ,  H01L29/16

CPC分类号： H01L27/088 ,  G01L9/0042 ,  G21C17/00 ,  H01L23/49838 ,  H01L24/48 ,  H01L29/1608 ,  H01L2224/48227 ,  H01L2924/10272 ,  H01L2924/1424

摘要： Provided is a SiC semiconductor element equipped with a SiC integrated circuit having a stable characteristic, which operates normally even in a radiation environment. A radiation resistant circuit device includes: a SiC semiconductor element equipped with a SiC integrated circuit, a printed board on which the SiC semiconductor element is provided, a conductive wiring that is arranged inside the printed board and has a predetermined surface facing a bottom surface of a substrate electrode of the SiC integrated circuit, and an insulating material arranged between the bottom surface of the substrate electrode of the SiC integrated circuit and the predetermined surface of the conductive wiring.

公开(公告)号：US20180240766A1

公开(公告)日：2018-08-23

申请号：US15833098

申请日：2017-12-06

申请人： Murata Manufacturing Co., Ltd.

发明人： Isao OBU ,  Yasunari Umemoto ,  Masahiro Shibata

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L29/20

CPC分类号： H01L24/05 ,  H01L21/30617 ,  H01L21/3083 ,  H01L21/76898 ,  H01L23/3157 ,  H01L24/32 ,  H01L29/06 ,  H01L29/20 ,  H01L2224/0346 ,  H01L2224/04026 ,  H01L2224/05011 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05164 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/26145 ,  H01L2224/29139 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2924/10158 ,  H01L2924/1424 ,  H01L2924/35121 ,  H01L2924/00014

摘要： A compound semiconductor substrate has a first main surface parallel to a first direction and a second direction perpendicular to the first direction, a second main surface located on a side opposite to the first main surface, and a recess. The recess has an opening, a bottom surface facing the opening, and a plurality of side surfaces located between the opening and the bottom surface. The side surfaces include at least one first side surface forming an angle of about θ degrees with the bottom surface in the recess and at least one second side surface forming an angle of about ϕ degrees with the bottom surface in the recess. The total length of edge lines between the first main surface and the at least one first side surface is larger than that of edge lines between the first main surface and the at least one second side surface.

公开(公告)号：US20240243100A1

公开(公告)日：2024-07-18

申请号：US18618790

申请日：2024-03-27

申请人： Rohm Co., Ltd.

发明人： Bungo TANAKA

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/10 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L25/0655 ,  H01L23/10 ,  H01L23/3135 ,  H01L23/49513 ,  H01L24/48 ,  H01L23/49541 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2924/1424 ,  H01L2924/14252

摘要： A semiconductor device includes a first semiconductor element formed with a step-down circuit, a first lead electrically connected to the first semiconductor element, and a second lead electrically connected to the first semiconductor element and spaced apart from the first lead in a first direction. The semiconductor device additionally includes a sealing resin covering the first semiconductor element and a portion of each of the first lead and the second lead. The sealing resin includes a recess formed between the first lead and the second lead in the first direction. As viewed in the first direction, the recess overlaps with the first lead and the second lead.

公开(公告)号：US12009307B2

公开(公告)日：2024-06-11

申请号：US17421460

申请日：2020-12-30

申请人： WUXI ESIONTECH CO., LTD.

发明人： Yueer Shan ,  Yanfeng Xu ,  Jicong Fan ,  Yanfei Zhang ,  Hua Yan

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17796

CPC分类号： H01L23/5381 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0652 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17796 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/14211 ,  H01L2924/1424 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/37001

摘要： The present application discloses a multi-die FPGA implementing a built-in analog circuit using an active silicon connection layer, and relates to the field of FPGA technology. The multi-die FPGA allows multiple small-scale and small-area dies to cascade to achieve large-scale and large-area FPGA products, reducing processing difficulties and improving chip production yields. Meanwhile, due to the existence of the active silicon connection layer, some circuit structures that are difficult to implement within the die and/or occupy a large die area and/or have a low processing requirement can be laid out in the silicon connection layer, solving the existing problems of making these circuit structures directly within the die. Part of the circuit structures can be implemented within the silicon connection layer and the rest in the die, which helps optimize the performance of FPGA products, improve system stability, and reduce system area.

公开(公告)号：US20180218921A1

公开(公告)日：2018-08-02

申请号：US15849065

申请日：2017-12-20

申请人： Murata Manufacturing Co., Ltd.

发明人： Kenichi SHIMAMOTO

IPC分类号： H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H03F3/195

CPC分类号： H01L21/563 ,  H01L23/49816 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/14051 ,  H01L2224/14519 ,  H01L2924/13051 ,  H01L2924/13054 ,  H01L2924/13091 ,  H01L2924/1424 ,  H03F3/195 ,  H03F2200/411 ,  H03F2200/451

摘要： A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and outputs a third signal, and a semiconductor substrate having a main surface parallel to a plane defined by first and second directions and which has the first and second transistors formed thereon. The main surface has thereon a first bump connected to a collector or drain of the first transistor, a second bump connected to an emitter or source of the first transistor, a third bump connected to a collector or drain of the second transistor, and a fourth bump connected to an emitter or source of the second transistor. The first bump is circular, the second through fourth bumps are rectangular or oval, and the area of each of the second through fourth bumps is larger than that of the first bump.

公开(公告)号：US20150270245A1

公开(公告)日：2015-09-24

申请号：US14641864

申请日：2015-03-09

申请人： Kabushiki Kaisha Toshiba

发明人： Hiroshi YAMADA

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/04 ,  H01L23/00 ,  H01L23/29

CPC分类号： H01L23/5386 ,  H01L21/568 ,  H01L23/295 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/1424 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/11

摘要： A semiconductor device according to an embodiment includes a first semiconductor unit including a plurality of first semiconductor chips, an organic resin provided between the first semiconductor chips, a wiring layer provided above the first semiconductor chips to electrically connect the first semiconductor chips to each other, and a plurality of connecting terminals provided on an upper portion of the wiring layer and a second semiconductor unit fixed to a wiring layer side of the first semiconductor unit, the second semiconductor unit fixed to a region sandwiched between the connecting terminals, the second semiconductor unit having a second semiconductor chip, the second semiconductor unit electrically connected to the first semiconductor unit.

摘要翻译： 根据实施例的半导体器件包括：第一半导体单元，包括多个第一半导体芯片;设置在第一半导体芯片之间的有机树脂，设置在第一半导体芯片上方以将第一半导体芯片彼此电连接的布线层， 以及设置在所述布线层的上部的多个连接端子和固定到所述第一半导体单元的布线层侧的第二半导体单元，所述第二半导体单元固定在夹在所述连接端子之间的区域，所述第二半导体单元 具有第二半导体芯片，所述第二半导体单元电连接到所述第一半导体单元。

公开(公告)号：US08080874B1

公开(公告)日：2011-12-20

申请号：US11855826

申请日：2007-09-14

申请人： Jeremy Werner ,  Daniel L. Rosenband ,  Jeremy Matthew Plunkett ,  William L. Schmidt ,  David T. Wang ,  Wael O. Zohni ,  Philip Arnold Ferolito ,  Michael John Sebastian Smith ,  Suresh Natarajan Rajan ,  Joseph C. Fjelstad

发明人： Jeremy Werner ,  Daniel L. Rosenband ,  Jeremy Matthew Plunkett ,  William L. Schmidt ,  David T. Wang ,  Wael O. Zohni ,  Philip Arnold Ferolito ,  Michael John Sebastian Smith ,  Suresh Natarajan Rajan ,  Joseph C. Fjelstad

IPC分类号： H01L23/34 ,  H01L23/48

CPC分类号： H05K1/181 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/5387 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/1424 ,  H01L2924/1436 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/0281 ,  H05K1/141 ,  H05K1/147 ,  H05K2201/10454 ,  H05K2201/10484 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/2018 ,  Y02P70/611 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system, method, and apparatus are included for providing additional space between an integrated circuit package and a circuit board. An integrated circuit package is provided including a plurality of integrated circuit package contacts. Also provided is a circuit board in electrical communication with the integrated circuit package. Further, the integrated circuit package, the integrated circuit contacts, and/or the circuit board is configured for providing additional space between the integrated circuit package and the circuit board to position at least a portion of at least one component between the integrated circuit package and the circuit board.

摘要翻译： 包括系统，方法和装置，用于在集成电路封装和电路板之间提供额外的空间。 提供了包括多个集成电路封装触点的集成电路封装。 还提供了与集成电路封装电通信的电路板。 此外，集成电路封装，集成电路触点和/或电路板被配置为在集成电路封装和电路板之间提供额外的空间，以将至少一部分的至少一部分置于集成电路封装和 电路板。