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    Early header CRC in data response packets with variable gap count
    1.
    发明申请
    Early header CRC in data response packets with variable gap count 审中-公开
    数据响应报文中的早期报头CRC可变间隙计数

    公开(公告)号：US20090271532A1

    公开(公告)日：2009-10-29

    申请号：US12108744

    申请日：2008-04-24

    申请人： Brian D. Allison ,  Wayne M. Barrett ,  Mark L. Rudquist ,  Kenneth M. Valk ,  Brian T. Vanderpool

    发明人： Brian D. Allison ,  Wayne M. Barrett ,  Mark L. Rudquist ,  Kenneth M. Valk ,  Brian T. Vanderpool

    IPC分类号： G06F13/14

    CPC分类号： G06F11/1004

    摘要： A method is provided for processing a command issued by a processor over a bus. The method includes (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet including the header and the header CRC; (4) loading a timer to run until data required to complete the command is received or the timer expires; and (5) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.

    摘要翻译： 提供了一种用于处理由总线发出的处理器的命令的方法。 该方法包括（1）将命令发送到远程节点以获得完成命令所需的数据; （2）从远程节点接收包括报头和报头CRC的响应分组; （3）验证包括报头和报头CRC的响应报文; （4）加载定时器运行，直到接收完成命令所需的数据或定时器到期; 和（5）在接收完成命令所需的数据之前，安排通过总线将数据返回给处理器。

    Reducing Memory Fetch Latency Using Next Fetch Hint
    2.
    发明申请
    Reducing Memory Fetch Latency Using Next Fetch Hint 审中-公开
    使用下一个提取提示减少内存提取延迟

    公开(公告)号：US20090271578A1

    公开(公告)日：2009-10-29

    申请号：US12108019

    申请日：2008-04-23

    申请人： Wayne M. Barrett ,  Brian T. Vanderpool

    发明人： Wayne M. Barrett ,  Brian T. Vanderpool

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0215 ,  G06F12/0862 ,  G06F2212/6028

    摘要： In one aspect, a processor is provided. The processor may include logic, coupled to the processor, and to issue a currently issued memory fetch over a processor bus. The currently issued memory fetch may include a next fetch hint that may include information about a next memory fetch.

    摘要翻译： 在一个方面，提供一种处理器。 处理器可以包括耦合到处理器的逻辑，并且通过处理器总线发布当前发布的存储器提取。 当前发行的存储器提取可以包括可以包括关于下一个存储器提取的信息的下一个提取提示。

    Early header CRC in data response packets with variable gap count
    3.
    发明申请
    Early header CRC in data response packets with variable gap count 审中-公开
    数据响应报文中的早期报头CRC可变间隙计数

    公开(公告)号：US20090268736A1

    公开(公告)日：2009-10-29

    申请号：US12108637

    申请日：2008-04-24

    申请人： Brian D. Allison ,  Wayne M. Barrett ,  Mark L. Rudquist ,  Kenneth M. Valk ,  Brian T. Vanderpool

    发明人： Brian D. Allison ,  Wayne M. Barrett ,  Mark L. Rudquist ,  Kenneth M. Valk ,  Brian T. Vanderpool

    IPC分类号： H04L12/56

    CPC分类号： H04L1/0061 ,  H04L1/0072 ,  H04L2001/0094

    摘要： A method is provided for processing commands issued by a processor over a bus. The method includes the steps of (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet based on the header CRC; and (4) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.

    摘要翻译： 提供了一种处理由总线发出的命令的方法。 该方法包括以下步骤：（1）将命令发送到远程节点以获得对完成命令所需的数据的访问; （2）从远程节点接收包括报头和报头CRC的响应分组; （3）基于报头CRC验证响应分组; 和（4）在接收完成命令所需的数据之前，安排通过总线将数据返回到处理器。

    Method, Apparatus, System and Program Product Supporting Directory-Assisted Speculative Snoop Probe With Concurrent Memory Access
    5.
    发明申请
    Method, Apparatus, System and Program Product Supporting Directory-Assisted Speculative Snoop Probe With Concurrent Memory Access 审中-公开
    方法，设备，系统和程序产品支持目录辅助的具有并发存储器访问的投机窥探探测器

    公开(公告)号：US20080244189A1

    公开(公告)日：2008-10-02

    申请号：US11693809

    申请日：2007-03-30

    申请人： Brian D. Allison ,  Wayne M. Barrett ,  Philip R. Hillier ,  Kenneth M. Valk ,  Brian T. Vanderpool

    发明人： Brian D. Allison ,  Wayne M. Barrett ,  Philip R. Hillier ,  Kenneth M. Valk ,  Brian T. Vanderpool

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0817 ,  G06F12/0882 ,  G06F2212/507

    摘要： A multiprocessor data processing system includes a memory controller controlling access to a memory subsystem, multiple processor buses coupled to the memory controller, and at least one of multiple processors coupled to each processor bus. In response to receiving a first read request of a first processor via a first processor bus, the memory controller initiates a speculative access to the memory subsystem and a lookup of the target address in a central coherence directory. In response to the central coherence directory indicating that a copy of the target memory block is cached by a second processor, the memory controller transmits a second read request for the target address on a second processor bus. In response to receiving a clean snoop response to the second read request, the memory controller provides to the first processor the target memory block retrieved from the memory subsystem by the speculative access.

    摘要翻译： 多处理器数据处理系统包括控制对存储器子系统的访问的存储器控​​制器，耦合到存储器控制器的多个处理器总线以及耦合到每个处理器总线的多个处理器中的至少一个。 响应于经由第一处理器总线接收到第一处理器的第一读取请求，存储器控制器启动对存储器子系统的推测访问以及在中央一致性目录中查找目标地址。 响应于指示目标存储器块的副本被第二处理器缓存的中央一致性目录，存储器控制器在第二处理器总线上发送针对目标地址的第二读取请求。 响应于对第二读取请求接收到干净的窥探响应，存储器控制器通过投机访问向第一处理器提供从存储器子系统检索的目标存储器块。

    Disparity reduction for high speed serial links
    6.
    发明授权
    Disparity reduction for high speed serial links 有权
    高速串行链路的差距缩小

    公开(公告)号：US08823558B2

    公开(公告)日：2014-09-02

    申请号：US13599196

    申请日：2012-08-30

    申请人： Wayne M. Barrett

    发明人： Wayne M. Barrett

    IPC分类号： H03M5/00 ,  H03M13/00 ,  H03M13/31

    CPC分类号： H03M13/00 ,  H03M13/31 ,  H04L49/1507

    摘要： System, computer program product, and computer-implemented method to improve a running disparity of an encoded bit stream in a distributed network switch, the distributed network switch comprising a plurality of switch modules including a first switch module, by receiving, at the first switch module, a raw data stream comprising a plurality of bits, receiving a bit sequence, encoding at least a first bit of the raw data stream using a corresponding at least a first bit of the bit sequence, transmitting the encoded first bit, inverting the first bit of the bit sequence, and encoding a second bit of the raw data stream using the inverted first bit.

    摘要翻译： 系统，计算机程序产品和计算机实现的方法来改进分布式网络交换机中编码比特流的运行差异，所述分布式网络交换机包括多个交换模块，包括第一交换模块，通过在第一交换机 模块，包括多个比特的原始数据流，接收比特序列，使用比特序列的对应的至少第一比特对原始数据流的至少第一比特进行编码，发送编码的第一比特，将第一比特反转 比特序列，并且使用倒置的第一比特对原始数据流的第二比特进行编码。

    Apparatus and method for burst data transfer employing a pause at fixed data intervals
    7.
    发明授权
    Apparatus and method for burst data transfer employing a pause at fixed data intervals 失效
    用于以固定数据间隔进行暂停的突发数据传输的装置和方法

    公开(公告)号：US5584033A

    公开(公告)日：1996-12-10

    申请号：US335228

    申请日：1994-11-07

    申请人： Wayne M. Barrett ,  Bruce L. Beukema ,  William E. Hammer ,  Daniel F. Moertl

    发明人： Wayne M. Barrett ,  Bruce L. Beukema ,  William E. Hammer ,  Daniel F. Moertl

    IPC分类号： G06F13/28 ,  G06F13/36 ,  G06F13/42 ,  H04L29/08

    CPC分类号： G06F13/28 ,  G06F13/4226

    摘要： A plurality of devices attached to a communications bus observe a burst transfer protocol which allows pausing only at pre-determined, fixed intervals of n data words, where a word is the width of the bus. In accordance with this protocol, once burst transfer is initialized the sending device transmits an uninterrupted stream of n data words over the communications bus, after which either the sender or receiver may cause transmission to pause. The sender may need to wait for more data, or the receiver may need to finish processing the data just received. The pause lasts as long as needed until both devices are ready to proceed. This cycle is repeated until the data transmission is complete. The sending and receiving devices do not relinquish control of the bus during a pause, and therefore are not required to re-initialize communications. In the preferred embodiment, after n data words have been transmitted, the sender and receiver toggle interlocking signals that accomplish a handshaking between the two devices. The sender de-activates its signal when it is ready to send more, and the receiver de-activates its signal when it is ready to receive more. Both devices are equipped with buffers large enough to hold n data words, but the buffers need not be as large as the longest possible burst communication.

    摘要翻译： 连接到通信总线的多个设备观察突发传输协议，该协议允许仅以n个数据字的预定的固定间隔暂停，其中一个字是总线的宽度。 根据该协议，一旦突发传送被初始化，发送设备通过通信总线发送不间断的n个数据字流，之后发送者或接收者可能导致传输暂停。 发送方可能需要等待更多的数据，否则接收方可能需要完成处理刚收到的数据。 暂停持续时间长，直到两台设备都准备好继续。 重复此循环，直到数据传输完成。 发送和接收设备在暂停期间不放弃总线的控制，因此不需要重新初始化通信。 在优选实施例中，在发送n个数据字之后，发送器和接收器切换在两个装置之间完成握手的互锁信号。 当准备好发送更多信号时，发送器取消激活其信号，当接收器准备好接收信号时，接收器会取消激活信号。 两个设备都配备有足够大的缓冲器以容纳n个数据字，但缓冲器不需要像最长可能的突发通信一样大。

    Early HSS Rx data sampling
    8.
    发明授权
    Early HSS Rx data sampling 失效
    早期HSS Rx数据采样

    公开(公告)号：US07735032B2

    公开(公告)日：2010-06-08

    申请号：US11860616

    申请日：2007-09-25

    申请人： Wayne M. Barrett ,  Todd A. Greenfield

    发明人： Wayne M. Barrett ,  Todd A. Greenfield

    IPC分类号： G06F17/50

    CPC分类号： G06F13/385 ,  H03K5/135 ,  H03M9/00

    摘要： A design structure includes a data communication circuit to facilitate communication between a deserializer, responsive to a serial data stream, which puts data onto a parallel bus, and a device that is in data communication therewith. The circuit a deserialization clock that asserts a clock read pulse each time data on the parallel bus is valid. A delay unit asserts a corresponding delayed clock pulse. The delayed clock pulse is delayed from the clock read pulse by a predetermined period. A clock tree repeats the delayed clock pulse and periodically asserts a plurality of end point repeated clock pulses, each of which has a substantially simultaneous leading edge. The predetermined amount of time is selected so as to cause each of the end point repeated clock signals to be asserted when data on the parallel bus is valid, thereby enabling the device to read data from the parallel bus.

    摘要翻译： 一种设计结构包括数据通信电路，用于响应于将数据放入并行总线的串行数据流以及与其进行数据通信的设备，解串器之间的通信。 每个数据并行总线上的时序读取脉冲的反序列化时钟的电路都是有效的。 延迟单元断言相应的延迟时钟脉冲。 延迟时钟脉冲从时钟读取脉冲延迟预定周期。 时钟树重复延迟的时钟脉冲，并且周期性地确定多个重复的时钟脉冲，其中每一个具有基本上同时的前沿。 选择预定量的时间，以便当并行总线上的数据有效时使每个端点重复的时钟信号被断言，从而使得设备能够从并行总线读取数据。

    Early high speed serializer-deserializer (HSS)internal receive (Rx) interface for data sampling clock signals on parallel bus
    10.
    发明授权
    Early high speed serializer-deserializer (HSS)internal receive (Rx) interface for data sampling clock signals on parallel bus 有权
    早期高速串行器 - 解串器（HSS）内部接收（Rx）接口，用于并行总线上的数据采样时钟信号

    公开(公告)号：US07454543B2

    公开(公告)日：2008-11-18

    申请号：US11380240

    申请日：2006-04-26

    申请人： Wayne M. Barrett ,  Todd A. Greenfield

    发明人： Wayne M. Barrett ,  Todd A. Greenfield

    IPC分类号： G06F17/50 ,  G06F13/38

    CPC分类号： G06F13/385 ,  H03K5/135 ,  H03M9/00

    摘要： In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units is valid on the parallel bus. A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted.

    摘要翻译： 在用于以并行格式从串行数据源读取数据的方法中，来自串行数据源的数据通过将多个预定义的数据单元放置在并行总线上而反序列化，并且当多个预定义单元中的每一个单元 在并行总线上有效。 延迟时钟脉冲在每次断言反序列化时钟之后产生预定的时间量。 重复每个延迟脉冲，以便产生对应于每个延迟脉冲的终点重复时钟脉冲，其中预定量的时间是确保每个终点重复时并行总线上的每个预定义的数据单元有效的时间量 时钟脉冲被断言。