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13 条记录 (耗时 0.037 秒)

    Method of fabricating a plurality of gate structures
    4.
    发明授权
    Method of fabricating a plurality of gate structures 有权
    制造多个门结构的方法

    公开(公告)号：US08334198B2

    公开(公告)日：2012-12-18

    申请号：US13085029

    申请日：2011-04-12

    申请人： Jian-Hao Chen ,  Wei-Yang Lee ,  Wei-Yeh Tang ,  Xiong-Fei Yu ,  Kuang-Yuan Hsu

    发明人： Jian-Hao Chen ,  Wei-Yang Lee ,  Wei-Yeh Tang ,  Xiong-Fei Yu ,  Kuang-Yuan Hsu

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/6659 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/7833

    摘要： The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.

    摘要翻译： 本发明涉及集成电路制造，更具体地涉及具有多个栅极结构的半导体器件。 制造多个栅极结构的示例性方法包括提供硅衬底; 在衬底上沉积虚拟氧化物层; 在虚拟氧化物层上沉积虚拟栅电极层; 图案化层以限定多个虚拟门; 在所述多个虚拟栅极上形成含氮侧壁间隔物; 在所述含氮侧壁间隔件之间形成层间电介质层; 通过原子层沉积（ALD）工艺在层间介质层上选择性地沉积硬掩模层; 去除虚拟栅极电极层; 去除虚拟氧化物层; 沉积栅极电介质; 并沉积栅电极。

    Method of fabricating high-k/metal gate device
    7.
    发明授权
    Method of fabricating high-k/metal gate device 有权
    制造高k /金属栅极器件的方法

    公开(公告)号：US08334197B2

    公开(公告)日：2012-12-18

    申请号：US12639630

    申请日：2009-12-16

    申请人： Da-Yuan Lee ,  Kuang-Yuan Hsu ,  Xiong-Fei Yu ,  Wei-Yang Lee ,  Matt Yeh

    发明人： Da-Yuan Lee ,  Kuang-Yuan Hsu ,  Xiong-Fei Yu ,  Wei-Yang Lee ,  Matt Yeh

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/28185 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    摘要： The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench.

    摘要翻译： 本公开提供了一种方法，其包括提供半导体衬底; 在所述半导体衬底上形成栅极结构，所述第一栅极结构包括设置在所述虚拟电介质上的虚设电介质和虚设栅极; 从栅极结构去除伪栅极和虚设电介质，从而形成沟槽; 形成部分填充沟槽的高k电介质层; 在部分填充沟槽的高k电介质层上形成阻挡层; 在所述阻挡层上形成部分填充所述沟槽的覆盖层; 进行退火处理; 去除覆盖层; 在所述阻挡层上形成填充在所述沟槽的其余部分中的金属层; 并进行化学机械抛光（CMP）以去除沟槽外的各种层。

    METHOD OF FABRICATING HIGH-K/METAL GATE DEVICE
    8.
    发明申请
    METHOD OF FABRICATING HIGH-K/METAL GATE DEVICE 有权
    制造高K /金属栅极器件的方法

    公开(公告)号：US20110143529A1

    公开(公告)日：2011-06-16

    申请号：US12639630

    申请日：2009-12-16

    申请人： Da-Yuan Lee ,  Kuang-Yuan Hsu ,  Xiong-Fei Yu ,  Wei-Yang Lee ,  Matt Yeh

    发明人： Da-Yuan Lee ,  Kuang-Yuan Hsu ,  Xiong-Fei Yu ,  Wei-Yang Lee ,  Matt Yeh

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28185 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    摘要： The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench.

    摘要翻译： 本公开提供了一种方法，其包括提供半导体衬底; 在所述半导体衬底上形成栅极结构，所述第一栅极结构包括设置在所述虚拟电介质上的虚设电介质和虚设栅极; 从栅极结构去除伪栅极和虚设电介质，从而形成沟槽; 形成部分填充沟槽的高k电介质层; 在部分填充沟槽的高k电介质层上形成阻挡层; 在所述阻挡层上形成部分填充所述沟槽的覆盖层; 进行退火处理; 去除覆盖层; 在所述阻挡层上形成填充在所述沟槽的其余部分中的金属层; 并进行化学机械抛光（CMP）以去除沟槽外的各种层。

    METHODS FOR A GATE REPLACEMENT PROCESS
    9.
    发明申请
    METHODS FOR A GATE REPLACEMENT PROCESS 有权
    门更换过程的方法

    公开(公告)号：US20110081774A1

    公开(公告)日：2011-04-07

    申请号：US12575280

    申请日：2009-10-07

    申请人： Matt Yeh ,  Hui Ouyang ,  Da-Yuan Lee ,  Kuang Yuan Hsu ,  Hun-Jan Tao ,  Xiong-Fei Yu

    发明人： Matt Yeh ,  Hui Ouyang ,  Da-Yuan Lee ,  Kuang Yuan Hsu ,  Hun-Jan Tao ,  Xiong-Fei Yu

    IPC分类号： H01L21/28

    CPC分类号： H01L29/401 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66545

    摘要： A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.

    摘要翻译： 公开了一种制造半导体器件的方法。 在一个实施例中，该方法可以包括提供衬底; 在所述衬底上形成包括第一虚拟栅极的栅极结构; 从栅极结构去除第一伪栅极以形成沟槽; 形成界面层，高k电介质层和覆盖层以部分地填充在沟槽中; 在所述覆盖层上形成第二虚拟栅极，其中所述第二伪栅极填充所述沟槽; 并用金属栅极替换第二虚拟栅极。 在一个实施例中，该方法可以包括提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在所述高k电介质层上形成蚀刻停止层; 在所述蚀刻停止层上形成包括低热预算硅的覆盖层; 在覆盖层上形成虚拟栅极层; 形成栅极结构; 并进行门更换处理。

    Methods for a gate replacement process
    10.
    发明授权
    Methods for a gate replacement process 有权
    门更换过程的方法

    公开(公告)号：US08367563B2

    公开(公告)日：2013-02-05

    申请号：US12575280

    申请日：2009-10-07

    申请人： Matt Yeh ,  Hui Ouyang ,  Da-Yuan Lee ,  Kuang Yuan Hsu ,  Hun-Jan Tao ,  Xiong-Fei Yu

    发明人： Matt Yeh ,  Hui Ouyang ,  Da-Yuan Lee ,  Kuang Yuan Hsu ,  Hun-Jan Tao ,  Xiong-Fei Yu

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/401 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66545

    摘要： A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.

    摘要翻译： 公开了一种制造半导体器件的方法。 在一个实施例中，该方法可以包括提供衬底; 在所述衬底上形成包括第一虚拟栅极的栅极结构; 从栅极结构去除第一伪栅极以形成沟槽; 形成界面层，高k电介质层和覆盖层以部分地填充在沟槽中; 在所述覆盖层上形成第二虚拟栅极，其中所述第二伪栅极填充所述沟槽; 并用金属栅极替换第二虚拟栅极。 在一个实施例中，该方法可以包括提供衬底; 在衬底上形成界面层; 在界面层上形成高k电介质层; 在所述高k电介质层上形成蚀刻停止层; 在所述蚀刻停止层上形成包括低热预算硅的覆盖层; 在覆盖层上形成虚拟栅极层; 形成栅极结构; 并进行门更换处理。