公开(公告)号：US09355874B2

公开(公告)日：2016-05-31

申请号：US13244337

申请日：2011-09-24

申请人： Weibo Yu ,  Hsueh-Chin Lu ,  Han-Guan Chew ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

发明人： Weibo Yu ,  Hsueh-Chin Lu ,  Han-Guan Chew ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC分类号： C03C15/00 ,  H01L21/67 ,  H01L21/311

CPC分类号： H01L21/6708 ,  H01L21/31111

摘要： A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture.

摘要翻译： 公开了在单晶片蚀刻装置中实现的单晶片蚀刻装置和各种方法。 在一个实施例中，在单晶片蚀刻装置中蚀刻氮化硅层包括：将磷酸加热至第一温度; 将硫酸加热至第二温度; 混合加热的磷酸和加热的硫酸; 将磷酸/硫酸混合物加热至第三温度; 并用加热的磷酸/硫酸混合物蚀刻氮化硅层。

公开(公告)号：US20130078809A1

公开(公告)日：2013-03-28

申请号：US13244337

申请日：2011-09-24

申请人： Weibo Yu ,  Hsueh-Chin Lu ,  Han-Guan Chew ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

发明人： Weibo Yu ,  Hsueh-Chin Lu ,  Han-Guan Chew ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC分类号： H01L21/306

CPC分类号： H01L21/6708 ,  H01L21/31111

摘要： A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture.

摘要翻译： 公开了在单晶片蚀刻装置中实现的单晶片蚀刻装置和各种方法。 在一个实施例中，在单晶片蚀刻装置中蚀刻氮化硅层包括：将磷酸加热到第一温度; 将硫酸加热至第二温度; 混合加热的磷酸和加热的硫酸; 将磷酸/硫酸混合物加热至第三温度; 并用加热的磷酸/硫酸混合物蚀刻氮化硅层。

公开(公告)号：US08932962B2

公开(公告)日：2015-01-13

申请号：US13442040

申请日：2012-04-09

申请人： Weibo Yu ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

发明人： Weibo Yu ,  Kuo Bin Huang ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC分类号： H01L21/302

CPC分类号： H01L21/6708 ,  H01L21/30608 ,  H01L21/31111 ,  H01L21/67109 ,  H01L22/12 ,  H01L22/20

摘要： A method and apparatus for dispensing a liquid etchant onto a wafer dispenses the liquid etchant onto a wafer using a scanning dispensing nozzle while controlling the dispensing temperature of the etchant in real time as a function of the radial position of the dispensing nozzle over the wafer. The dispensing temperature of the etchant is controlled to enhance the effectiveness of the etchant and thus compensate for the lower etching rate zones in the wafer.

摘要翻译： 用于将液体蚀刻剂分配到晶片上的方法和设备使用扫描分配喷嘴将液体蚀刻剂分配到晶片上，同时根据分配喷嘴在晶片上的径向位置实时控制蚀刻剂的分配温度。 控制蚀刻剂的分配温度以提高蚀刻剂的有效性，从而补偿晶片中较低的蚀刻速率区域。

公开(公告)号：US20130330906A1

公开(公告)日：2013-12-12

申请号：US13490635

申请日：2012-06-07

申请人： Weibo Yu ,  Ming-His Yeh ,  Chih-Tang Peng ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Syun-Ming Jang

发明人： Weibo Yu ,  Ming-His Yeh ,  Chih-Tang Peng ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L29/66795

摘要： A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.

摘要翻译： 公开了制造半导体IC的方法。 该方法包括接收设备。 该器件包括半导体衬底，半导体衬底中的翅片之间的多个散热片和沟槽。 该方法还包括用介电材料填充沟槽以形成浅沟槽隔离（STI），对介电材料施加低热预算退火，以及对电介质材料进行湿法处理。

公开(公告)号：US08735252B2

公开(公告)日：2014-05-27

申请号：US13490635

申请日：2012-06-07

申请人： Weibo Yu ,  Ming-Hsi Yeh ,  Chih-Tang Peng ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Syun-Ming Jang

发明人： Weibo Yu ,  Ming-Hsi Yeh ,  Chih-Tang Peng ,  Hao-Ming Lien ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC分类号： H01L21/336

CPC分类号： H01L21/76224 ,  H01L29/66795

摘要： A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.

摘要翻译： 公开了制造半导体IC的方法。 该方法包括接收设备。 该器件包括半导体衬底，半导体衬底中的翅片之间的多个散热片和沟槽。 该方法还包括用介电材料填充沟槽以形成浅沟槽隔离（STI），对介电材料施加低热预算退火，以及对电介质材料进行湿法处理。

公开(公告)号：US20070040188A1

公开(公告)日：2007-02-22

申请号：US11207450

申请日：2005-08-19

申请人： Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

发明人： Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC分类号： H01L31/00

CPC分类号： H01L21/76897 ,  H01L21/76804 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.

摘要翻译： 集成电路芯片包括缓冲层，下层，电介质层，空穴和阻挡层。 缓冲层位于底层之上。 电介质层在缓冲层之上。 孔形成并延伸穿过介电层和缓冲层，并向下层开放。 该孔包括在缓冲层处的缓冲层部分和介电层处的电介质层部分。 孔的缓冲层部分的至少一部分具有比孔的电介质层部分的最小横截面面积更大的横截面面积。 保形阻挡层覆盖孔中的介电层和缓冲层的表面。 孔是通孔或接触孔，其后面填充有导电材料以形成导电通孔或导电接触。

公开(公告)号：US20110049567A1

公开(公告)日：2011-03-03

申请号：US12841763

申请日：2010-07-22

申请人： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

发明人： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66636

摘要： The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.

摘要翻译： 本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域 在硅衬底中，对硅衬底中的凹部进行无偏压蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中形成半导体材料 在硅衬底中。 一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。 实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。 一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。 因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。

公开(公告)号：US09054130B2

公开(公告)日：2015-06-09

申请号：US12841763

申请日：2010-07-22

申请人： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

发明人： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

IPC分类号： H01L21/302 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66636

摘要： The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.

摘要翻译： 本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域 在硅衬底中，对硅衬底中的凹陷区域进行非偏置蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中生长半导体材料 在硅衬底中。 一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。 实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。 一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。 因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。

公开(公告)号：US07511349B2

公开(公告)日：2009-03-31

申请号：US11207450

申请日：2005-08-19

申请人： Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

发明人： Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76897 ,  H01L21/76804 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.

摘要翻译： 集成电路芯片包括缓冲层，下层，电介质层，空穴和阻挡层。 缓冲层位于底层之上。 电介质层在缓冲层之上。 孔形成并延伸穿过介电层和缓冲层，并向下层开放。 该孔包括在缓冲层处的缓冲层部分和介电层处的电介质层部分。 孔的缓冲层部分的至少一部分具有比孔的电介质层部分的最小横截面面积更大的横截面面积。 保形阻挡层覆盖孔中的介电层和缓冲层的表面。 孔是通孔或接触孔，其后面填充有导电材料以形成导电通孔或导电接触。

公开(公告)号：US6027861A

公开(公告)日：2000-02-22

申请号：US44763

申请日：1998-03-20

申请人： Chen-Hua Yu ,  Syun-Ming Jang ,  Chao-Cheng Chen

发明人： Chen-Hua Yu ,  Syun-Ming Jang ,  Chao-Cheng Chen

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/768 ,  G03F7/20 ,  H01L21/027

CPC分类号： H01L21/76855 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/0332 ,  H01L21/31116

摘要： A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses high resolution DUV photolithography. By using a thin layer of photoresist to pattern a hardmask, full advantage of the high resolution can be attained. The hardmask in turn, is sufficiently durable to withstand subsequent etching of the insulative layer. The methods taught by this invention are of particular value for the formation of contacts to semiconductive devices although they are also applied to forming via openings. DUV photoresists having thicknesses of less than 500 nm are used with a DUV stepper. The hardmask materials include Ti/TiN and amorphous silicon. Etching selectivities of these materials with respect to typical insulative materials used in integrated circuit manufacture are of the order of 50:1.

摘要翻译： 描述了用于在接触和通孔的绝缘层中蚀刻二分之一微米开口的方法。 该方法采用高分辨率DUV光刻技术。 通过使用薄层的光致抗蚀剂来模拟硬掩模，可以获得高分辨率的全部优点。 依次进行硬掩模，足够耐用以承受绝缘层的后续蚀刻。 本发明教导的方法对于形成与半导体器件的接触具有特别的价值，尽管它们也用于形成通孔。 使用厚度小于500nm的DUV光刻胶与DUV步进器一起使用。 硬掩模材料包括Ti / TiN和非晶硅。 相对于集成电路制造中使用的典型绝缘材料，这些材料的蚀刻选择性为50：1。