公开(公告)号：US09601421B2

公开(公告)日：2017-03-21

申请号：US13976356

申请日：2011-12-30

申请人： Weng Hong Teh ,  Deepak V. Kulkarni

发明人： Weng Hong Teh ,  Deepak V. Kulkarni

IPC分类号： H01L23/498 ,  H01L23/00 ,  H05K3/46 ,  H05K3/00

CPC分类号： H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/3511 ,  H05K3/0097 ,  H05K3/4682 ,  H05K2201/10674 ,  H01L2924/00

摘要： An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a primary core adjacent at least a pair of the lateral sidewalls of the die; and a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die. A method of forming a package and an apparatus including a computing device including a package are also disclosed.

公开(公告)号：US20140217599A1

公开(公告)日：2014-08-07

申请号：US13976356

申请日：2011-12-30

申请人： Weng Hong Teh ,  Deepak V. Kulkarni

发明人： Weng Hong Teh ,  Deepak V. Kulkarni

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/3511 ,  H05K3/0097 ,  H05K3/4682 ,  H05K2201/10674 ,  H01L2924/00

摘要： An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a primary core adjacent at least a pair of the lateral sidewalls of the die; and a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die. A method of forming a package and an apparatus including a computing device including a package are also disclosed.

摘要翻译： 一种包括模具的装置，包括第一侧和相对的第二侧，包括具有限定模具的厚度的接触点和侧壁的装置侧; 与芯片的至少一对侧壁相邻的主芯; 以及耦合到所述管芯的第二侧的堆积载体，所述堆积载体包括导电材料和绝缘材料的多个交替层，其中所述导电材料层中的至少一个耦合到所述触点之一 点的死亡 还公开了一种形成包装的方法和包括包括包装的计算装置的装置。

公开(公告)号：US20110159310A1

公开(公告)日：2011-06-30

申请号：US12655407

申请日：2009-12-30

申请人： Deepak V. Kulkarni ,  Carl L. Deppisch ,  Leonel R. Arana ,  Gregory S. Constable ,  Sriram Srinivasan

发明人： Deepak V. Kulkarni ,  Carl L. Deppisch ,  Leonel R. Arana ,  Gregory S. Constable ,  Sriram Srinivasan

IPC分类号： B32B15/04 ,  B23K31/02 ,  B32B38/00

CPC分类号： B23K1/0016 ,  B23K1/20 ,  B23K1/203 ,  B23K3/085 ,  H01L23/3675 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/16251 ,  Y10T428/12222

摘要： Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.

摘要翻译： 形成封装结构的方法和相关结构包括在IHS的阻焊剂开口位置上形成低熔点焊料材料，从而在非SRO保护区域内形成密封剂; 将IHS连接到密封剂上，并固化密封剂，其中在IHS和低熔点焊料材料之间形成焊接接头。

公开(公告)号：US09254532B2

公开(公告)日：2016-02-09

申请号：US12655407

申请日：2009-12-30

申请人： Deepak V. Kulkarni ,  Carl L. Deppisch ,  Leonel R. Arana ,  Gregory S. Constable ,  Sriram Srinivasan

发明人： Deepak V. Kulkarni ,  Carl L. Deppisch ,  Leonel R. Arana ,  Gregory S. Constable ,  Sriram Srinivasan

IPC分类号： H01L23/02 ,  H01L23/12 ,  H01L23/10 ,  H01L23/34 ,  B23K1/00 ,  B23K3/08

CPC分类号： B23K1/0016 ,  B23K1/20 ,  B23K1/203 ,  B23K3/085 ,  H01L23/3675 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/16251 ,  Y10T428/12222

摘要： Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.

摘要翻译： 形成封装结构的方法和相关结构包括在IHS的阻焊剂开口位置上形成低熔点焊料材料，从而在非SRO保护区域内形成密封剂; 将IHS连接到密封剂上，并固化密封剂，其中在IHS和低熔点焊料材料之间形成焊接接头。

公开(公告)号：US20140138845A1

公开(公告)日：2014-05-22

申请号：US13684110

申请日：2012-11-21

申请人： Deepak V. Kulkarni ,  Russell K. Mortensen ,  John S. Guzek

发明人： Deepak V. Kulkarni ,  Russell K. Mortensen ,  John S. Guzek

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L23/5389 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L28/40 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2224/92224 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate comprising a plurality of build-up layers, such as BBUL. In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.

摘要翻译： 本公开的实施例涉及包装组件，以及用于形成包装组件和包含包装组件的系统的方法。 封装组件可以包括包括多个堆积层的衬底，例如BBUL。 在各种实施例中，电路由特征可以设置在衬底的外表面上。 在各种实施例中，主逻辑管芯和第二管芯或电容器可以嵌入在多个堆积层中。 在各种实施例中，可以在多个积层中定义电路径，以便绕过主逻辑管芯来路由第二管芯或电容器之间的电功率或接地信号与电路径特征。