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15 条记录 (耗时 0.035 秒)

    Multi-well time-lapse nodal analysis of transient production systems
    1.
    发明授权
    Multi-well time-lapse nodal analysis of transient production systems 有权
    瞬时生产系统的多时间延时节点分析

    公开(公告)号：US08788252B2

    公开(公告)日：2014-07-22

    申请号：US13281152

    申请日：2011-10-25

    申请人： Wentao Zhou ,  Raj Banerjee ,  Eduardo Proano ,  Ji Li ,  Yinli Wang ,  Peng Fang ,  Nelson Bolanos ,  R. K. Michael Thambynayagam ,  Gregory P. Grove ,  Jeffrey B. Spath

    发明人： Wentao Zhou ,  Raj Banerjee ,  Eduardo Proano ,  Ji Li ,  Yinli Wang ,  Peng Fang ,  Nelson Bolanos ,  R. K. Michael Thambynayagam ,  Gregory P. Grove ,  Jeffrey B. Spath

    IPC分类号： G06G7/48

    CPC分类号： E21B43/00

    摘要： A method, apparatus and program product utilize an analytical reservoir simulator to perform inflow simulation for a node during nodal analysis in a multi-well petroleum production system. By doing so, time-lapse nodal analysis may be performed of a transient production system in a multi-well context, often taking into account production history and the transient behavior of a reservoir system. Moreover, in some instances, an interference effect from different wells in a multi-well production system may be considered, and in some instances nodal analysis may be performed simultaneously for multiple wells. Multi-layer nodal analysis may also be performed in some instances to account for the pressure loss in a wellbore between multiple layers.

    摘要翻译： 一种方法，装置和程序产品利用分析储层模拟器在多井石油生产系统中的节点分析期间对节点进行流入模拟。 通过这样做，可以在多井环境中对瞬时生产系统进行延时节点分析，通常考虑到油藏系统的生产历史和瞬态特性。 此外，在一些情况下，可以考虑来自多井生产系统中的不同井的干扰效应，并且在一些情况下，可以针对多个井同时进行节点分析。 在某些情况下也可以执行多层节点分析，以解决多层之间的井眼中的压力损失。

    Assessing plasma induced gate dielectric degradation with stress induced leakage current measurements
    4.
    发明授权
    Assessing plasma induced gate dielectric degradation with stress induced leakage current measurements 失效
    用应力诱发的漏电流测量评估等离子体诱导的栅介质劣化

    公开(公告)号：US6043102A

    公开(公告)日：2000-03-28

    申请号：US924129

    申请日：1997-09-05

    申请人： Peng Fang ,  Jiang Tao

    发明人： Peng Fang ,  Jiang Tao

    IPC分类号： H01L21/66

    CPC分类号： H01L22/12

    摘要： Plasma induced degradation of thin gate dielectric layers, e.g., silicon dioxide layers of less than 50 .ANG., is assessed by impressing a constant current density across the gate dielectric layer and measuring the resulting stress induced leakage current as a function of time. The sensitivity of the stress induced leakage current to traps generated in a thin gate dielectric layer enables the use of stress induced leakage current measurements to monitor plasma induced damage during various phases of semiconductor manufacturing.

    摘要翻译： 通过在栅极电介质层上施加恒定的电流密度并测量作为时间的函数的所得到的应力诱发的漏电流来评估薄栅介质层（例如小于50的二氧化硅层）的等离子体诱导的降解。 应力感应漏电流对薄栅极电介质层产生的阱产生的敏感性使得能够使用应力感应泄漏电流测量来监测半导体制造的各个阶段期间的等离子体引起的损伤。

    Interlevel dielectric with multiple air gaps between conductive lines of an integrated circuit
    5.
    发明授权
    Interlevel dielectric with multiple air gaps between conductive lines of an integrated circuit 失效
    集成电路的导线之间具有多个气隙的层间电介质

    公开(公告)号：US5994776A

    公开(公告)日：1999-11-30

    申请号：US63481

    申请日：1998-04-20

    申请人： Peng Fang ,  Homi Fatemi

    发明人： Peng Fang ,  Homi Fatemi

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

    摘要： A method of forming low dielectric insulation between pairs of conductive lines separated by insulating material of a level of interconnection for integrated circuits by selectively removing portions of the insulating material to create spaces for containing a gas with a dielectric constant of slightly above 1. Preferably, the insulating material is a conformal source of silicon oxide, such as tetraethylorthosilicate. The resultant method forms an insulation separating the conductive lines whose composite dielectric constant with the gas in the spaces between the insulating material is not greater than about 3 over a predetermined distance. An integrated circuit having a plurality of semiconductor devices being interconnected by conductive lines separated by insulating material and spaces containing a gas, composite dielectric constant of which is not greater than about 3 over a predetermined distance.

    摘要翻译： 通过选择性地去除绝缘材料的部分以产生用于容纳介电常数略高于1的气体的空间，形成由用于集成电路的互连级别的绝缘材料隔开的导电线之间的低介电绝缘的方法。优选地， 绝缘材料是氧化硅的保形源，例如原硅酸四乙酯。 所得到的方法形成绝缘体，其绝缘材料的绝缘材料的复合介电常数与绝缘材料之间的间隔不大于约3°的预定距离的导线。 一种具有多个半导体器件的集成电路，其通过由绝缘材料隔开的导线和包含气体的空间互相连接，复合介电常数在预定距离以上不大于约3。

    Test system and methodology to improve stacked NAND gate based critical path performance and reliability
    7.
    发明授权
    Test system and methodology to improve stacked NAND gate based critical path performance and reliability 失效
    测试系统和方法，以提高堆叠NAND门的关键路径性能和可靠性

    公开(公告)号：US06216099B1

    公开(公告)日：2001-04-10

    申请号：US08924090

    申请日：1997-09-05

    申请人： Peng Fang ,  Sunil Shabde

    发明人： Peng Fang ,  Sunil Shabde

    IPC分类号： G06F1750

    CPC分类号： G01R31/31704

    摘要： A test system and methodology to improve the performance and reliability of critical paths including stacked NAND gates with sub-minimum channel transistors employs one or more inverter based ring oscillators to generate reliability data. The reliability data is used to calibrate an aged transistor model, which describes the hot carrier reliability of sub-minimum channel length transistors. A computer simulation uses the calibrated, aged transistor model to simulate the critical path circuitry including the stacked NAND gates.

    摘要翻译： 提高关键路径的性能和可靠性的测试系统和方法，包括具有次最小通道晶体管的堆叠NAND门采用一个或多个基于逆变器的环形振荡器来产生可靠性数据。 可靠性数据用于校准老化的晶体管模型，其描述了次最小沟道长度晶体管的热载流子可靠性。 计算机模拟使用经校准的老化晶体管模型来模拟包括堆叠NAND门的关键路径电路。

    Method for determining a reliable oxide thickness
    8.
    发明授权
    Method for determining a reliable oxide thickness 失效
    确定可靠的氧化物厚度的方法

    公开(公告)号：US6133746A

    公开(公告)日：2000-10-17

    申请号：US163414

    申请日：1998-09-30

    申请人： Peng Fang ,  Hao Fang

    发明人： Peng Fang ,  Hao Fang

    IPC分类号： G01N27/92 ,  H01L23/544 ,  G01R31/12 ,  H01L21/66

    CPC分类号： H01L22/34 ,  G01N27/92

    摘要： A method for determining a reliable gate oxide thickness for a transistor involves subjecting test transistors to an alternating current (AC) voltage until the test transistors break down. The breakdown times of the test transistors are measured and correlated with the corresponding gate oxide thickness of the test transistor to form a reliability model of the transistor. The reliable gate oxide thickness is determined by extrapolating the reliability model out to a predetermined period of time for which reliability is desired, for example, ten years.

    摘要翻译： 用于确定晶体管的可靠栅极氧化物厚度的方法包括使测试晶体管经受交流（AC）电压，直到测试晶体管分解为止。 测量测试晶体管的击穿时间并与测试晶体管的相应栅极氧化物厚度相关联，以形成晶体管的可靠性模型。 可靠的栅极氧化物厚度通过将可靠性模型推断到需要可靠性的预定时间段（例如十年）来确定。