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252 条记录 (耗时 0.051 秒)

    Tri-level-cell DRAM and sense amplifier with alternating offset voltage
    9.
    发明授权
    Tri-level-cell DRAM and sense amplifier with alternating offset voltage 有权
    具有交替偏置电压的三电平单元DRAM和读出放大器

    公开(公告)号：US09478277B1

    公开(公告)日：2016-10-25

    申请号：US14844003

    申请日：2015-09-03

    申请人： Bo Liu

    发明人： Bo Liu

    IPC分类号： G11C11/401 ,  G11C11/4096 ,  G11C11/56

    CPC分类号： G11C11/4096 ,  G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/565 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5634

    摘要： Tri-level-cell dynamic random access memory (DRAM) stores 3 levels of voltage (0, VDD/2, VDD) into a plurality of memory cells. Selected memory cell connected to bitline (BLT) to develop signal voltage, and adjacent reference bitline (BLR) develops reference voltage at VDD/2. An asymmetrical sensing amplifier (ASA), which has alternative positive offset and negative offset, is used to sense signal voltage and reference voltage for both their difference and sameness. ASA control signals, A and B, switch at different timing points or at different voltage level or the combination of both to have offset voltage set at either positive or negative polarity. Two consecutive read out from one ASA or one single read out from two ASA can be implemented to read memory cells data to local IOs. Output from ASA will be used to restore voltage back to the accessed memory cells.

    摘要翻译： 三电平单元动态随机存取存储器（DRAM）将3级电压（0，VDD / 2，VDD）存储到多个存储单元中。 连接到位线（BLT）的选定存储单元产生信号电压，并且相邻的参考位线（BLR）产生VDD / 2的参考电压。 具有替代正偏移和负偏移的不对称感测放大器（ASA）用于检测信号电压和参考电压两者的差异和相同性。 ASA控制信号A和B在不同的定时点或不同的电压电平下进行切换，或者两者的组合使偏移电压设置为正或负极性。 可以实现从一个ASA或两个ASA读取的两个连续读出，以将内存单元数据读取到本地IO。 来自ASA的输出将用于将电压恢复到访问的存储单元。

    Method of preventing auto-doping during epitaxial layer growth by cleaning the reaction chamber with hydrogen chloride
    10.
    发明授权
    Method of preventing auto-doping during epitaxial layer growth by cleaning the reaction chamber with hydrogen chloride 有权
    通过用氯化氢清洗反应室来防止外延层生长期间的自掺杂的方法

    公开(公告)号：US09334583B2

    公开(公告)日：2016-05-10

    申请号：US13202944

    申请日：2011-06-27

    申请人： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

    发明人： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

    IPC分类号： C30B25/02 ,  C30B25/18 ,  C30B29/06 ,  C30B23/02 ,  H01L21/02

    CPC分类号： C30B25/186 ,  C30B23/025 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02661

    摘要： An epitaxial growth method for preventing auto-doping effect is presented. This method starts with the removal of impurities from the semiconductor substrate and the reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling. This method can prevent auto-doping effect during the epitaxial growth on semiconductor substrate and thus ensure the performance and enhance the reliability of the devices in peripheral circuit region.

    摘要翻译： 提出了一种防止自动掺杂效应的外延生长方法。 该方法首先从要使用的半导体衬底和反应室中除去杂质。 然后，在从半导体衬底的表面脱离的掺杂剂原子的提取之前，将半导体衬底装载在清洁的反应室中，以在真空条件下预烘烤。 接下来，在高温低气流条件下，在所述半导体衬底的表面上形成第一本征外延层。 接下来，在低温和高气体流动条件下，在生长的本征外延层的结构表面上形成所需厚度的第二外延层。 最后，冷却后硅片卸载。 该方法可以防止在半导体衬底上的外延生长期间的自掺杂效应，从而确保外围电路区域中器件的性能和可靠性。