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1.发明授权System for exception recovery using a conditional substitution instruction which inserts a replacement result in the destination of the excepting instruction 失效使用条件替换指令进行异常恢复的系统，该指令将替换结果插入到除外指令的目的地
公开(公告)号：US5596733A
公开(公告)日：1997-01-21
申请号：US361874
申请日：1994-12-22
CPC分类号： G06F9/30076 , G06F11/0721 , G06F11/0793 , G06F9/3861 , G06F9/3877
摘要： A conditional substitution instruction is provided in an instruction set of a computer system to correct exceptions occurring during run-time. The conditional substitution instruction can be executed concurrently in a pipelined computer system with a potentially excepting instruction, or simultaneously in a wide computer system. The conditional substitution instruction substitutes a default value for the result of the potentially excepting instruction if the potentially excepting instruction produces one or more specified exceptions.
摘要翻译： 在计算机系统的指令集中提供条件替换指令，以纠正在运行期间发生的异常。 条件替换指令可以在具有潜在的除外指令的流水线计算机系统中同时执行，也可以在宽计算机系统中同时执行。 如果潜在的除外指令产生一个或多个指定的异常，条件替换指令将代替潜在的除外指令的结果的默认值。
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公开(公告)号：US5689653A
公开(公告)日：1997-11-18
申请号：US384308
申请日：1995-02-06
CPC分类号： G06F9/30043 , G06F15/8084 , G06F9/30036 , G06F9/3455 , G06F9/383
摘要： The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.
摘要翻译： 通过提供一个或多个向量缓冲器来减轻计算机系统的操作码带宽限制。 数据在存储器和处理器寄存器之间使用向量缓冲区在两部分进程中传输。 在第一部分中，向量请求指令通过将数据存储在识别存储器中的一组数据元素（矢量）的控制寄存器中来发起数据的缓冲。 当识别信息被加载到控制寄存器中时，向量预取控制器在存储器和向量缓冲器之间传送向量的元素。 在第二部分中，向量元素操作指令将矢量的下一个元素传送到矢量缓冲器和指定的处理器寄存器之间，用于算术或逻辑运算。
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3.发明授权Method and system for deferring exceptions generated during speculative execution 失效用于推迟在投机执行期间产生的异常的方法和系统
公开(公告)号：US5692169A
公开(公告)日：1997-11-25
申请号：US324940
申请日：1994-10-18
申请人： Vinod K. Kathail , Rajiv Gupta , Bantwal R. Rau , Michael S. Schlansker , William S. Worley, Jr. , Frederic C. Amerson
发明人： Vinod K. Kathail , Rajiv Gupta , Bantwal R. Rau , Michael S. Schlansker , William S. Worley, Jr. , Frederic C. Amerson
CPC分类号： G06F9/3865 , G06F9/30072 , G06F9/30181 , G06F9/30189 , G06F9/3842
摘要： A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.
摘要翻译： 支持投机执行的方法包括将操作指定为投机或非投机性，然后推迟由投机操作产生的异常，同时立即通过非投机操作报告异常。 如果推测操作使用产生异常的推测操作的结果，则会传播该异常。 使用检查操作检测和报告延期异常，并将其合并到非推测操作中或作为单独检查操作插入。 用于支持推测执行的系统包括用于识别投机操作并推迟由这种操作产生的任何异常的功能单元。 功能单元可以通过存储指示在寄存器文件中发生错误的信息来延迟异常。 要检查延迟异常，功能单元然后读取寄存器文件。
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4.发明授权Out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control issurance of instructions from the queues 失效使用队列中的指令之间的编码相关性来确定停止值，从而控制排队指令的发布，从而执行乱序执行
公开(公告)号：US5941983A
公开(公告)日：1999-08-24
申请号：US881244
申请日：1997-06-24
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3838 , G06F9/3869 , G06F9/3885
摘要： A method for executing instructions out-of-order to improve performance of a processor includes compiling the instructions of a program into separate queues along with encoded dependencies between instructions in the different queues. The processor then issues instructions from each of these queues independently, except that it enforces the encoded dependencies among instructions from different queues. If an instruction is dependent on instructions in other queues, the processor waits to issue it until the instructions on which it depends are issued. The processor includes a stall unit, comprised of a number of instruction counters for each queue, that enforces the dependencies between instructions in different queues.
摘要翻译： 用于执行无序的指令以改善处理器的性能的方法包括将程序的指令与不同队列中的指令之间的编码的依赖关系一起编译成单独的队列。 然后处理器独立地从每个这些队列发出指令，除了它强制来自不同队列的指令之间的编码依赖性。 如果指令依赖于其他队列中的指令，则处理器等待发出，直到发出依赖于其的指令。 该处理器包括一个停顿单元，包括用于每个队列的多个指令计数器，其强制在不同队列中的指令之间的依赖性。
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5.发明授权Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations 失效在数据寄存器中传播异常状态的方法和系统，以及用非投机操作检测投机操作的异常
公开(公告)号：US5778219A
公开(公告)日：1998-07-07
申请号：US597784
申请日：1996-02-07
申请人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , B. Ramakrishna Rau , Michael S. Schlansker , William S. Worley, Jr.
发明人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , B. Ramakrishna Rau , Michael S. Schlansker , William S. Worley, Jr.
CPC分类号： G06F9/3865 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3863
摘要： A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file. If an exception is detected, then the exception is processed and one or more of the speculative operation are re-executed (in a non-speculative mode) where necessary to process the exception.
摘要翻译： 支持投机执行的方法包括将操作指定为投机或非投机性，然后推迟由投机操作产生的异常，同时立即通过非投机操作报告异常。 如果推测操作使用产生异常的推测操作的结果，则会传播该异常。 使用检查操作检测和报告延期异常，并将其合并到非推测操作中或作为单独检查操作插入。 用于支持推测执行的系统包括用于识别投机操作并推迟由这种操作产生的任何异常的功能单元。 功能单元可以通过存储指示在寄存器文件中发生错误的信息来延迟异常。 要检查延迟异常，功能单元然后读取寄存器文件。 如果检测到异常，则处理异常，并且在需要处理异常的情况下重新执行一个或多个推测操作（以非推测模式）。
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6.发明授权Information processing apparatus with prefetch control for prefetching data structure from memory through cache memory 失效具有预取控制的信息处理装置，用于通过高速缓冲存储器从存储器预取数据结构
公开(公告)号：US5721865A
公开(公告)日：1998-02-24
申请号：US588503
申请日：1996-01-18
申请人： Yooichi Shintani , Yoshikazu Tanaka , Naohiko Irie , William S. Worley, Jr. , B. Ramakrishna Rau , Rajiv Gupta , Frederic C. Amerson
发明人： Yooichi Shintani , Yoshikazu Tanaka , Naohiko Irie , William S. Worley, Jr. , B. Ramakrishna Rau , Rajiv Gupta , Frederic C. Amerson
CPC分类号： G06F9/3455 , G06F9/30047 , G06F9/30181 , G06F9/383 , G06F9/3834
摘要： To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.
摘要翻译： 为了改进用于预取由处理器访问的数据的电路的功能，预取单元在其中结合有用于发出读取需要预取的一组数据的请求的电路，并且用于保存响应于读取读取的数据组的寄存器 请求。 在高速缓存请求单元的控制下，从高速缓冲存储器或主存储器读出数据组。 可以预取多组数据。 当进行数据指定时，处理器请求高速缓冲存储器读取要预取的数据所属的块。 预取单元中还包括一个电路，其中当处理器随后更新预取的数据时，其更新的数据变为无效。 也可以读出结构中的向量复合体的元素，例如索引向量等。 也可以处理处理器内产生的中断。
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公开(公告)号：US5933850A
公开(公告)日：1999-08-03
申请号：US843795
申请日：1997-04-21
CPC分类号： G06F9/3808 , G06F12/0875 , G06F9/30149 , G06F9/30178 , G06F9/322 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853 , G06F9/3863
摘要： An instruction cache which separates storage cells for instruction data from storage cells for sequence control is disclosed. Instructions are decoded prior to being stored to the instruction cache which serves a primary cache, while prior hierarchical levels of memory store instructions in an encoded form. Because the instructions have a variable-length, the instruction cache includes a next address determination circuit to determine the next instruction address. The invention is advantageous because the separation of storage cells enables a next instruction address to be generated during a fetch stage for a current instruction, thereby avoiding the need for an otherwise necessary additional decoding stage. A bypass mechanism useful for any cache following a cache miss is also disclosed.
摘要翻译： 公开了一种从用于序列控制的存储单元分离用于指令数据的存储单元的指令高速缓存。 指令在被存储到服务于主缓存的指令高速缓存之前被解码，而先前的层次级别的存储器以编码形式存储指令。 由于指令具有可变长度，所以指令高速缓存包括下一个地址确定电路以确定下一个指令地址。 本发明是有利的，因为存储单元的分离使得能够在当前指令的获取阶段期间产生下一个指令地址，从而避免了对另外必需的附加解码级的需要。 还公开了对于高速缓存未命中之后的任何高速缓存有用的旁路机制。
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8.发明授权High definition scintillation detector for medicine, homeland security and non-destructive evaluation 有权高清晰度闪烁检测仪，用于医药，国土安全和无损评估公开(公告)号：US08477906B2
公开(公告)日：2013-07-02
申请号：US12529867
申请日：2008-03-05
摘要： A bundle of drawn fibers that have X-ray scintillating unagglommerated nanocrystallite particles in plastic or glass cores of down to 0.1 micron spacing and claddings of X-ray absorbing compounds in the cladding composition. Optional is a cover to the bundle that blocks light from leaving the bundle at the X-ray side while allowing X-rays to pass into the cores. To image the light exiting the fiber bundle at the sub-micron level, light expansion is preferable using either a lens system or a fiber bundle expander.
摘要翻译： 一束拉伸纤维，其在包层组合物中具有低至0.1微米间距的塑料或玻璃芯中具有X射线闪烁的未散射的纳米晶粒和X射线吸收化合物的包层。 可选的是捆绑的封面，阻止光线在X射线侧离开束，同时允许X射线进入核心。 为了在亚微米级别对离开纤维束的光进行成像，使用透镜系统或纤维束扩张器优选进行光膨胀。
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公开(公告)号：US08171266B2
公开(公告)日：2012-05-01
申请号：US09922551
申请日：2001-08-02
申请人： Alan H. Karp , Rajiv Gupta
发明人： Alan H. Karp , Rajiv Gupta
IPC分类号： G06F12/00
CPC分类号： G06F9/3842 , G06F9/383
摘要： A method for look-ahead load pre-fetching that reduces the effects of instruction stalls caused by high latency instructions. Look-ahead load pre-fetching is accomplished by searching an instruction stream for load memory instructions while the instruction stream is stalled waiting for completion of a previous instruction in the instruction stream. A pre-fetch operation is issued for each load memory instruction found. The pre-fetch operations cause data for the corresponding load memory instructions to be copied to a cache, thereby avoiding long latencies in the subsequent execution of the load memory instructions.
摘要翻译： 一种用于预先加载预取的方法，可减少由高延迟指令引起的指令停顿的影响。 通过在指令流停止等待指令流中的先前指令的完成的情况下，通过搜索指令流来执行加载存储器指令来实现预先加载预取。 为发现的每个加载存储器指令发出预取操作。 预取操作导致相应的加载存储器指令的数据被复制到高速缓存，从而避免后续执行加载存储器指令的长时间延迟。
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公开(公告)号：US08010991B2
公开(公告)日：2011-08-30
申请号：US12018103
申请日：2008-01-22
申请人： Sekhar Sarukkai , Rajiv Gupta , Raghavendra Prasad
发明人： Sekhar Sarukkai , Rajiv Gupta , Raghavendra Prasad
CPC分类号： G06F21/6218 , G06F21/6236 , H04L63/10 , H04L63/20
摘要： An externalized entitlement management system comprises a policy administration point that is configured to receive one or more definitions or updates of entitlement policies specifying subjects, actions, and resources, and to update a first entitlement repository coupled to the policy administration point with the definitions or updates in response to receiving the definitions or updates; one or more policy decision points that are coupled to the policy administration point over a network; one or more policy enforcement points that are integrated into one or more respective first application programs, wherein each of the policy enforcement points is coupled to one of the policy decision points; and one or more action handlers in the policy administration point, wherein each of the action handlers is configured to intercept a particular action represented in an update to an entitlement policy, to transform the action into an entitlement update in a form compatible with a native entitlement mechanism of a second application program that does not have one of the policy enforcement points, to send the transformed entitlement update to the second application program, and to cause a rollback of the update of the first entitlement repository if the second application program fails to implement the entitlement update in the native entitlement mechanism.
摘要翻译： 外部化权利管理系统包括被配置为接收指定主题，动作和资源的授权策略的一个或多个定义或更新的策略管理点，并且利用定义或更新来更新耦合到策略管理点的第一授权存储库 响应于接收定义或更新; 通过网络耦合到策略管理点的一个或多个策略决策点; 一个或多个策略执行点被集成到一个或多个相应的第一应用程序中，其中每个策略执行点被耦合到策略决策点之一; 以及策略管理点中的一个或多个动作处理程序，其中每个动作处理程序被配置为拦截在授权策略的更新中表示的特定动作，以将操作转换为与本机授权相兼容的形式的授权更新 第二应用程序的机制，其不具有策略执行点之一，将转换的授权更新发送到第二应用程序，并且如果第二应用程序未能实现，则导致第一授权库的更新的回滚 本机授权机制中的权利更新。
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