公开(公告)号：US20100099250A1

公开(公告)日：2010-04-22

申请号：US12255329

申请日：2008-10-21

申请人： Woo Jin Jang ,  Sung Dong Cho ,  Bum Ki Moon

发明人： Woo Jin Jang ,  Sung Dong Cho ,  Bum Ki Moon

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05011 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01014 ,  H01L2224/05552

摘要： Methods of forming a contact pad include forming a copper pattern on a semiconductor substrate and forming a passivation layer on the copper pattern. The passivation layer is defined to have an opening therein that exposes at least a portion of an upper surface of the copper pattern. A diffusion barrier layer is formed in the opening by electroless plating the diffusion barrier layer onto the exposed portion of the upper surface of the copper pattern. This diffusion barrier layer operates as a barrier to copper out-diffusion from the copper pattern. These methods further include conformally depositing an underbump metallization layer onto at least a sidewall of the opening in the passivation layer and onto an upper surface of the diffusion barrier layer. A step is then performed to plate a contact bump (e.g., solder bump) onto a portion of the underbump metallization layer extending opposite the diffusion barrier layer.

摘要翻译： 形成接触焊盘的方法包括在半导体衬底上形成铜图案并在铜图案上形成钝化层。 钝化层被限定为在其中具有暴露铜图案的上表面的至少一部分的开口。 通过将扩散阻挡层化学镀在铜图案的上表面的暴露部分上，在开口中形成扩散阻挡层。 该扩散阻挡层作为从铜图案向铜扩散的屏障起作用。 这些方法进一步包括在钝化层中的开口的至少一个侧壁上并在扩散阻挡层的上表面上共形沉积下凸块金属化层。 然后执行步骤以将接触凸起（例如，焊料凸块）平铺到与扩散阻挡层相对延伸的下凸块金属化层的一部分上。

公开(公告)号：US07879720B2

公开(公告)日：2011-02-01

申请号：US12241744

申请日：2008-09-30

申请人： Woo Jin Jang ,  Sung Dong Cho ,  Hyung Woo Kim ,  Bum Ki Moon

发明人： Woo Jin Jang ,  Sung Dong Cho ,  Hyung Woo Kim ,  Bum Ki Moon

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/76804 ,  H01L21/76805 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer.

摘要翻译： 形成电互连的方法包括在半导体衬底上形成铜图案，然后在铜图案上形成电绝缘覆盖层，以及在电绝缘覆盖层上形成层间绝缘层。 然后形成接触孔，其延伸穿过层间绝缘层和电绝缘覆盖层并暴露铜图案的上表面。 然后执行化学镀步骤以在铜图案的暴露的上表面上形成铜图案延伸。 铜图案延伸部的厚度可以小于可以形成为SiCN层的电绝缘覆盖层的厚度。

公开(公告)号：US20100081272A1

公开(公告)日：2010-04-01

申请号：US12241744

申请日：2008-09-30

申请人： Woo Jin Jang ,  Sung Dong Cho ,  Hyung Woo Kim ,  Bum Ki Moon

发明人： Woo Jin Jang ,  Sung Dong Cho ,  Hyung Woo Kim ,  Bum Ki Moon

IPC分类号： H01L21/768

CPC分类号： H01L21/76804 ,  H01L21/76805 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer.

摘要翻译： 形成电互连的方法包括在半导体衬底上形成铜图案，然后在铜图案上形成电绝缘覆盖层，以及在电绝缘覆盖层上形成层间绝缘层。 然后形成接触孔，其延伸穿过层间绝缘层和电绝缘覆盖层并暴露铜图案的上表面。 然后执行化学镀步骤以在铜图案的暴露的上表面上形成铜图案延伸。 铜图案延伸部的厚度可以小于可以形成为SiCN层的电绝缘覆盖层的厚度。

公开(公告)号：US07381468B2

公开(公告)日：2008-06-03

申请号：US10920456

申请日：2004-08-18

申请人： Kyung Wook Paik ,  Kyung Woon Jang ,  Sung Dong Cho

发明人： Kyung Wook Paik ,  Kyung Woon Jang ,  Sung Dong Cho

IPC分类号： B32B27/38 ,  C08L63/00

CPC分类号： H01G4/206 ,  H05K1/162 ,  H05K2201/0209 ,  Y10T29/417 ,  Y10T428/24917 ,  Y10T428/31511

摘要： A polymer/ceramic composite paste for an embedded capacitor includes an organic solvent, a ceramic powder having a particle diameter of not more than 20 μm dispersed in the organic solvent, a polymer and a hardener. The use of the polymer/ceramic composite paste enables the formation of a dielectric layer having a high dielectric constant. The polymer/ceramic composite paste can be applied by a screen printing technique and is planarized to locally form a polymer/ceramic composite dielectric layer having a thickness of, e.g., up to 20 μm on a desired region. Accordingly, electrical parasitics resulting from the formation of a capacitor on unwanted regions can be reduced, and the capacitance error can be reduced.

摘要翻译： 用于嵌入式电容器的聚合物/陶瓷复合糊剂包括有机溶剂，分散在有机溶剂中的粒径不大于20μm的陶瓷粉末，聚合物和硬化剂。 使用聚合物/陶瓷复合糊剂能够形成具有高介电常数的介电层。 聚合物/陶瓷复合浆料可以通过丝网印刷技术施加，并且被平坦化以局部形成在所需区域上具有例如至多20μm的厚度的聚合物/陶瓷复合介电层。 因此，可以减少在不想要的区域上形成电容器所引起的电寄生现象，并且可以减小电容误差。