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    SUBSTRATE BONDING METHOD
    1.
    发明申请
    SUBSTRATE BONDING METHOD 审中-公开
    基板接合方法

    公开(公告)号：US20130118672A1

    公开(公告)日：2013-05-16

    申请号：US13615813

    申请日：2012-09-14

    申请人： Ho Joon Park ,  Kyung Wook Paik ,  Young Jae Kim ,  Seung Ho Kim ,  Ki Won Lee

    发明人： Ho Joon Park ,  Kyung Wook Paik ,  Young Jae Kim ,  Seung Ho Kim ,  Ki Won Lee

    IPC分类号： H05K3/00

    CPC分类号： H05K3/323 ,  B29C65/08 ,  H05K3/361 ,  H05K2201/09845 ,  Y10T156/10

    摘要： Disclosed herein is a substrate bonding method including stacking a plurality of bonding objects including anisotropic conductive films (ACFs) and flexible printed circuit boards (FPCBs), which are sequentially stacked, on a substrate including bonding surfaces having a plurality of steps, according to the plurality of steps of the bonding surfaces of the substrate, and pressurizing the plurality of bonding objects to the substrate by a bonding tool of a bonding unit having pressurization surfaces having a shape corresponding to the bonding surfaces of the substrate to bond the plurality of bonding objects to each other.

    摘要翻译： 这里公开了一种基板接合方法，其包括将包括各向异性导电膜（ACF）和顺序堆叠的柔性印刷电路板（FPCB）的多个粘结物体堆叠在包括具有多个台阶的接合表面的基板上，根据 通过具有与基板的接合面形状对应的加压面的接合单元的接合工具将多个接合体加压到基板上，以接合多个接合体 对彼此。

    Image sensor module and method thereof
    3.
    发明申请
    Image sensor module and method thereof 有权
    图像传感器模块及其方法

    公开(公告)号：US20060252246A1

    公开(公告)日：2006-11-09

    申请号：US11395157

    申请日：2006-04-03

    申请人： Kyung-Wook Paik ,  Myung-Jin Yim ,  Ho-Young Son ,  Yong-Min Kwon

    发明人： Kyung-Wook Paik ,  Myung-Jin Yim ,  Ho-Young Son ,  Yong-Min Kwon

    IPC分类号： H01L21/44

    CPC分类号： H01L31/02162 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14625 ,  H01L27/14632 ,  H01L27/14687 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

    摘要： The present invention relates to an image sensor module and a manufacturing method thereof, especially to a wafer level chip size package (WL-CSP) realized by directly contacting an image sensor chip wafer to a glass wafer on which an IR filter coating layer is deposited, an electrode rearrangement and a dicing process, a miniaturized image sensor module using this wafer level chip size package (WL-CSP) and a method thereof. The CMOS image sensor module using a wafer level chip size package technology according to the present invention comprises: an image sensor chip wafer having a partition with a lattice structure formed at portions except an image sensing area; and a glass wafer with an IR filter coating layer and a metal electrode; and wherein the image sensor chip wafer and the glass wafer form an electric contact and a chip sealing by a flip-chip bonding; and wherein a solder bump and a non solder bump are formed after a metal wiring is rearranged on a lower surface of the glass wafer. According to the present invention, it is possible to realize a cheap wafer level chip size package (WL-CSP) using the existing wafer processing and the metal deposition processing equipments. Further, an image sensor module with smaller thickness and area than the existing CSP package can be realized. Moreover, an image sensor module with a smaller area than the existing COG package can be realized.

    摘要翻译： 图像传感器模块及其制造方法技术领域本发明涉及一种图像传感器模块及其制造方法，特别涉及通过将图像传感器芯片晶片直接接触到其上沉积有IR滤光器涂层的玻璃晶片实现的晶片级芯片尺寸封装（WL-CSP） ，电极重排和切割处理，使用该晶片级芯片尺寸封装（WL-CSP）的小型化图像传感器模块及其方法。 使用根据本发明的晶片级芯片尺寸封装技术的CMOS图像传感器模块包括：图像传感器芯片晶片，具有形成在除了图像感测区域之外的部分处的格子结构的分隔; 和具有IR滤光器涂层和金属电极的玻璃晶片; 并且其中所述图像传感器芯片晶片和所述玻璃晶片通过倒装芯片接合形成电接触和芯片密封; 并且其中在金属布线重新布置在玻璃晶片的下表面上之后形成焊料凸块和非焊料凸点。 根据本发明，可以使用现有的晶片处理和金属沉积处理设备来实现廉价的晶片级芯片尺寸封装（WL-CSP）。 此外，可以实现具有比现有CSP封装更小的厚度和面积的图像传感器模块。 此外，可以实现具有比现有COG封装小的面积的图像传感器模块。

    Method for fabricating chip size packages using lamination process
    4.
    发明授权
    Method for fabricating chip size packages using lamination process 失效
    使用层压工艺制造芯片尺寸封装的方法

    公开(公告)号：US5879964A

    公开(公告)日：1999-03-09

    申请号：US105055

    申请日：1998-06-26

    申请人： Kyung Wook Paik ,  Se Young Jang

    发明人： Kyung Wook Paik ,  Se Young Jang

    IPC分类号： H01L23/28 ,  H01L23/31 ,  H01L21/44

    CPC分类号： H01L23/3114 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351

    摘要： A method for fabricating chip size packages which uses a lamination process, thereby not only achieving an improvement in the reliability of final electronic products, a reduction in the manufacturing costs, and a mass production resulting in a high marketability, but also being applicable to the fabrication of packages for both memory and non-memory chips and enabling the final electronic products to have high electronic performance while making the package size of the final electronic products not greater than 1.2 times the semiconductor chip size. The method includes the steps of cutting a wafer into a plurality of wafer strips each having several dies, arranging the wafer strips on an adhesive-coated polymer film supported by an annular frame in such a manner that they are aligned with each other while being uniformly spaced from one another, bonding the aligned wafer strips to the polymer film in accordance with a lamination process, forming a polymer dam made of an epoxy-based polymer on the polymer film around a wafer region, forming an encapsulant encapsulating the wafer strips, forming a double laminated polymer film to encapsulate the chips as an alternative encapsulation method, forming via holes at positions respectively corresponding to pads of chips through the polymer film, forming an array of I/O pads for the chips, fusing solder balls to the I/O pads, and cutting several ten dies integrally formed in one lot into separate packages.

    摘要翻译： 一种用于制造使用层压工艺的芯片尺寸封装的方法，从而不仅实现了最终电子产品的可靠性的提高，制造成本的降低以及导致高市场化的批量生产，而且还适用于 制造用于存储器和非存储器芯片的封装，并且使最终的电子产品具有高电子性能，同时使得最终电子产品的封装尺寸不超过半导体芯片尺寸的1.2倍。 该方法包括以下步骤：将晶片切割成多个晶片条，每个晶片条具有多个管芯，将晶片条布置在由环形框架支撑的粘合剂涂覆的聚合物膜上，使得它们彼此对准，同时均匀 彼此间隔开，根据层压工艺将对准的晶片条粘合到聚合物膜上，在聚合物膜周围形成由环氧基聚合物制成的聚合物坝，形成封装晶片条的密封剂，形成 将芯片封装的双层叠聚合物膜作为替代的封装方法，在分别对应于通过聚合物膜的芯片焊盘的位置处形成通孔，形成用于芯片的I / O焊盘阵列，将焊球熔合到I / O焊盘，并将一批中的几十个模具整体切割成单独的封装。

    Polymer/ceramic composite paste for embedded capacitor and method for fabricating capacitor using same
    8.
    发明授权
    Polymer/ceramic composite paste for embedded capacitor and method for fabricating capacitor using same 失效
    用于嵌入式电容器的聚合物/陶瓷复合糊剂及其制造电容器的方法

    公开(公告)号：US07381468B2

    公开(公告)日：2008-06-03

    申请号：US10920456

    申请日：2004-08-18

    申请人： Kyung Wook Paik ,  Kyung Woon Jang ,  Sung Dong Cho

    发明人： Kyung Wook Paik ,  Kyung Woon Jang ,  Sung Dong Cho

    IPC分类号： B32B27/38 ,  C08L63/00

    CPC分类号： H01G4/206 ,  H05K1/162 ,  H05K2201/0209 ,  Y10T29/417 ,  Y10T428/24917 ,  Y10T428/31511

    摘要： A polymer/ceramic composite paste for an embedded capacitor includes an organic solvent, a ceramic powder having a particle diameter of not more than 20 μm dispersed in the organic solvent, a polymer and a hardener. The use of the polymer/ceramic composite paste enables the formation of a dielectric layer having a high dielectric constant. The polymer/ceramic composite paste can be applied by a screen printing technique and is planarized to locally form a polymer/ceramic composite dielectric layer having a thickness of, e.g., up to 20 μm on a desired region. Accordingly, electrical parasitics resulting from the formation of a capacitor on unwanted regions can be reduced, and the capacitance error can be reduced.

    摘要翻译： 用于嵌入式电容器的聚合物/陶瓷复合糊剂包括有机溶剂，分散在有机溶剂中的粒径不大于20μm的陶瓷粉末，聚合物和硬化剂。 使用聚合物/陶瓷复合糊剂能够形成具有高介电常数的介电层。 聚合物/陶瓷复合浆料可以通过丝网印刷技术施加，并且被平坦化以局部形成在所需区域上具有例如至多20μm的厚度的聚合物/陶瓷复合介电层。 因此，可以减少在不想要的区域上形成电容器所引起的电寄生现象，并且可以减小电容误差。

    Wafer level chip size package for CMOS image sensor module and manufacturing method thereof
    9.
    发明申请
    Wafer level chip size package for CMOS image sensor module and manufacturing method thereof 审中-公开
    CMOS图像传感器模块的晶片级芯片尺寸封装及其制造方法

    公开(公告)号：US20070054419A1

    公开(公告)日：2007-03-08

    申请号：US11513203

    申请日：2006-08-31

    申请人： Kyung-Wook Paik ,  Myung-Jin Yim ,  Ho-Young Son

    发明人： Kyung-Wook Paik ,  Myung-Jin Yim ,  Ho-Young Son

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14618 ,  H01L27/14625 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2924/00011 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/01033 ,  H01L2924/00014

    摘要： Disclosed is a wafer level chip size package for an image sensor module and a manufacturing method thereof, more particularly to a small size image sensor module characterized by a structure where a glass formed with an I/R cut-off filter (layer) is assembled onto an image sensor chip by a polymer partition wall and a solder bump is formed on an electrode of the rear side of a chip connected by a through-hole formed on each I/O electrode of an image sensor chip and a wafer level chip size package process for realizing the module. The method for manufacturing a wafer level chip size package for an image sensor module, the method comprises: bonding an image sensor wafer glass and a glass wafer to form a through-hole on the image sensor wafer; filling the through-hole formed on the image sensor wafer with an exciting material; and forming a solder bump at the end of the exciting material to be connected with the circuit formed PCB substrate. According to the present invention, the existing equipments for wafer processing and metal deposition are used. Therefore, it is possible to realize a cost-effective wafer level chip size package and an image sensor module having the minimum thickness in a thickness direction than the existing wafer level chip size package for image sensor and the same area as an image sensor chip.

    摘要翻译： 公开了一种用于图像传感器模块的晶片级芯片尺寸封装及其制造方法，更具体地涉及一种小型图像传感器模块，其特征在于其中组装有I / R截止滤光器（层）的玻璃被组装 通过聚合物分隔壁将图像传感器芯片放置在图像传感器芯片上，并且在通过形成在图像传感器芯片的每个I / O电极上的通孔连接的芯片的后侧的电极和晶片级芯片尺寸上形成焊料凸块 实现模块的包过程。 一种用于制造用于图像传感器模块的晶片级芯片尺寸封装的方法，所述方法包括：将图像传感器晶片玻璃和玻璃晶片接合以在所述图像传感器晶片上形成通孔; 用激励材料填充形成在图像传感器晶片上的通孔; 并在激励材料的端部形成焊料凸点以与所形成的PCB基板连接。 根据本发明，使用现有的晶片处理和金属沉积设备。 因此，可以实现具有成本效益的晶片级芯片尺寸封装和图像传感器模块，其厚度方向比图像传感器的现有晶片级芯片尺寸封装和与图像传感器芯片相同的区域具有最小厚度。

    Preparation method of anisotropic conductive adhesive for flip chip interconnection on organic substrate
    10.
    发明授权
    Preparation method of anisotropic conductive adhesive for flip chip interconnection on organic substrate 失效
    有机基板上倒装芯片互连的各向异性导电胶的制备方法

    公开(公告)号：US06238597B1

    公开(公告)日：2001-05-29

    申请号：US09506708

    申请日：2000-02-18

    申请人： Myung Jin Yim ,  Kyung Wook Paik

    发明人： Myung Jin Yim ,  Kyung Wook Paik

    IPC分类号： H01B122

    CPC分类号： H05K3/323 ,  H01B1/20 ,  H01B1/22 ,  H01L24/27 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/07811 ,  H05K2201/0209 ,  H05K2201/0239 ,  H05K2201/10674 ,  H01L2924/00

    摘要： Disclosed is a method of preparing anisotropic conductive adhesives for flip chip interconnection on organic substrates, in which an epoxy resin as a binder is mixed with a conductive material and a non-conductive material at room temperature for 3 hours and then, with a coupling agent and a curing agent at room temperature for 1 hour. The anisotropic conductive adhesives are endowed with the electrical conductivity of conventional anisotropic conductive films and the mechanical reliability of an underfill used in a solder flip chip, simultaneously. The ACA shows fast hardenability and excellent coating and screening properties. The adhesive is spread over a plastic printed circuit board into which a flip chip is then brought. The flip chip and the plastic substrate can be bonded to each other using heat and pressure. Also, it is applicable for low-price flip chips and chip size packaging as well as for relevant-assembly packaging.

    摘要翻译： 公开了一种制备用于有机衬底上的倒装芯片互连的各向异性导电粘合剂的方法，其中作为粘合剂的环氧树脂在室温下与导电材料和非导电材料混合3小时，然后用偶联剂 和固化剂在室温下1小时。 各向异性导电粘合剂同时具有常规各向异性导电膜的导电性和焊料倒装芯片中使用的底部填充材料的机械可靠性。 ACA显示出快速淬透性和优异的涂层和筛选性能。 粘合剂分布在塑料印刷电路板上，然后将倒装芯片带入其中。 倒装芯片和塑料基板可以使用热和压力彼此接合。 此外，它适用于低价格倒装芯片和芯片尺寸封装以及相关组装封装。