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    Efuse bank and associated anchor bits
    1.
    发明授权
    Efuse bank and associated anchor bits 有权

    公开(公告)号：US10978167B1

    公开(公告)日：2021-04-13

    申请号：US16806546

    申请日：2020-03-02

    Applicant: Xilinx, Inc.

    Inventor： James D. Wesselkamper ,  Edward S. Peterson ,  Jason J. Moore ,  Steven E. McNeil

    IPC: G11C17/00 ,  G11C17/16 ,  G11C17/18

    Abstract: A disclosed circuit arrangement includes a bank of efuse cells, first and second sense amplifiers coupled to input signals representing constant logic-1 and logic-0 values, respectively, a storage circuit, an efuse control circuit, and an efuse security circuit. The efuse control circuit inputs signals from the bank of efuse cells and signals that are output from the first and second sense amplifiers, and stores data representative of values of the signals in the storage circuit. The efuse security reads the data from the storage circuit and generates an alert signal having a state that indicates a security violation in response to data representative of the value of the signal from the first sense amplifier indicating a logic-0 value or data representative of the value of the signal from the second sense amplifier indicating a logic-1 value.

    Mixed storage of data fields
    2.
    发明授权
    Mixed storage of data fields 有权

    公开(公告)号：US11379580B1

    公开(公告)日：2022-07-05

    申请号：US16819864

    申请日：2020-03-16

    Applicant: Xilinx, Inc.

    Inventor： James D. Wesselkamper ,  Edward S. Peterson ,  Jason J. Moore ,  Steven E. McNeil ,  Roger D. Flateau, Jr. ,  Danny Tsung-Heng Wu ,  Boon Y. Ang

    IPC: G06F21/55 ,  G06F21/72 ,  H04L9/32 ,  G11C29/00 ,  G11C29/08

    Abstract: An array of non-volatile memory cells includes rows and columns. A volatile storage circuit provides addressable units of storage. A control circuit reads first type data and second type data from one or more of the rows and multiple ones of the columns of the array of non-volatile memory cells. The control circuit stores the first type data and second type data read from each row in one or more addressable units of storage of the volatile storage. A security circuit reads first data from the one or more of the addressable units of the volatile storage and selects from the first data, the second type data that includes one or more bits of each of the one or more of the addressable units. The security circuit performs an integrity check on the selected second type data, and generates an alert signal that indicates a security violation in response to failure of the integrity check.

    Glitch detector and test glitch generator
    3.
    发明授权
    Glitch detector and test glitch generator 有权

    公开(公告)号：US10466275B1

    公开(公告)日：2019-11-05

    申请号：US16022403

    申请日：2018-06-28

    Applicant: Xilinx, Inc.

    Inventor： Sandeep Vundavalli ,  Sree RKC Saraswatula ,  James D. Wesselkamper ,  Santosh Yachareni ,  Shidong Zhou ,  Anil Kumar Kandala

    IPC: G11C29/00 ,  G01R11/24 ,  G01R31/30 ,  G06F21/86 ,  G06F21/76 ,  G01R22/06

    Abstract: Apparatus and associated methods relate to a glitch detection circuit monitoring a duration that a selected fractional supply voltage is below a predetermined voltage threshold. The selected fractional supply voltage may be at the predetermined threshold when the supply voltage is between a valid circuit-supply voltage and a power-on circuit-reset (POR). A glitch detect signal may be generated, for example, when the monitored duration is greater than a predetermined duration threshold. A test glitch generator may generate a test glitch, for example, having selectable voltage and duration, which may be selectably applied to the glitch detection circuit to verify operation. Various exemplary glitch detection circuits may advantageously determine externally produced tampering attempts by detecting circuit-supply voltages and durations that meet specific selectable supply voltage and duration criteria, improving security of sensitive field programmable gate array (FPGA) data by taking protective action in response to the detection.

    Method of and circuit for generating a physically unclonable function
    4.
    发明授权
    Method of and circuit for generating a physically unclonable function 有权

    公开(公告)号：US10027492B1

    公开(公告)日：2018-07-17

    申请号：US15633321

    申请日：2017-06-26

    Applicant: Xilinx, Inc.

    Inventor： James D. Wesselkamper

    IPC: H04L9/32 ,  H03K19/003 ,  G11C29/52 ,  G11C29/06 ,  G11C11/41

    Abstract: A method of generating a physically unclonable function is described. The method comprises calculating a total variation associated with differences between a plurality of elements of an entropy source in an integrated circuit; calculating a global variation associated the plurality of elements of the entropy source; generating a local variation by removing the global variation associated with the plurality of elements from the total variation; and generating a unique signature based upon the generated local variation. A circuit for generating a physically unclonable function is also described.

    Incremental authentication for memory constrained systems
    6.
    发明授权
    Incremental authentication for memory constrained systems 有权

    公开(公告)号：US11216591B1

    公开(公告)日：2022-01-04

    申请号：US16439350

    申请日：2019-06-12

    Applicant: Xilinx, Inc.

    Inventor： Felix Burton ,  Krishna C. Patakamuri ,  James D. Wesselkamper

    IPC: G06F21/00 ,  G06F21/64 ,  H04L9/32

    Abstract: Apparatus and associated methods relate to authenticating a back-to-front-built configuration image. In an illustrative example, a circuit may include memory configured to store a signature S, a second hash H2, and a first data chunk C1. Signature S may be signed on a first hash H1. H1 may be the hash for H2 and C1. If signature S passes verification, a hash engine may perform hash functions on C1 and H2 to generate a hash H1′. H1′ may be compared with H1 to indicate whether C1 has been tampered with or not. By using the incremental authentication, a signature that appears at the beginning of the image may be extended to the entire image while only using a small internal buffer. Advantageously, internal buffer may only need to store two hashes Hi, Hi+1, and a data chunk Ci, or, a signature S, a hash Hi, and a data chunk Ci.

    Secure external key storage for programmable ICS
    7.
    发明授权
    Secure external key storage for programmable ICS 有权

    公开(公告)号：US10044514B1

    公开(公告)日：2018-08-07

    申请号：US14866712

    申请日：2015-09-25

    Applicant: Xilinx, Inc.

    Inventor： Edward S. Peterson ,  James D. Wesselkamper

    IPC: G06F11/30 ,  H04L9/32 ,  H04L9/14

    Abstract: The disclosure describes approaches for protecting a circuit design for a programmable integrated circuit (IC). A black key is generated from an input red key by a registration circuit implemented on the programmable IC, and the black key is stored in a memory circuit external to the programmable IC. The programmable IC is configured to implement a pre-configuration circuit, which inputs the black key from the memory circuit and generates the red key from the black key. A ciphertext circuit design is decrypted into a plaintext circuit design by the programmable IC using the red key, and the red key is erased from the programmable IC. The programmable IC is reconfigured with the plaintext circuit design.

    Protection against differential power analysis attacks involving initialization vectors
    10.
    发明授权
    Protection against differential power analysis attacks involving initialization vectors 有权

    公开(公告)号：US11582021B1

    公开(公告)日：2023-02-14

    申请号：US16690097

    申请日：2019-11-20

    Applicant: Xilinx, Inc.

    Inventor： James D. Wesselkamper ,  Nathan A. Menhorn ,  Jason J. Moore

    IPC: H04L9/06 ,  G11C11/56 ,  G11C17/14 ,  G11C17/16 ,  H04L9/00

    Abstract: Disclosed approaches for validating initialization vectors determining by a configuration control circuit whether or not an input initialization vector is within a range of valid initialization vectors. In response to determining that the initialization vector is within the range of valid initialization vectors, the configuration control circuit decrypts the ciphertext into plaintext using the input initialization vector and configures a memory circuit with the plaintext. In response to determining that the first initialization vector is outside the range of valid initialization vectors, the configuration control circuit signals that the first initialization vector is invalid.

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