公开(公告)号：US20240313781A1

公开(公告)日：2024-09-19

申请号：US18123160

申请日：2023-03-17

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE ,  Sagheer AHMAD ,  Trevor J. BAUER ,  Kenneth MA ,  David P. SCHULTZ ,  John O'DWYER ,  Richard W. SWANSON ,  Bhuvanachandran K. NAIR ,  Millind MITTAL

IPC: H03K19/17736 ,  G01R31/317 ,  H03K19/0175 ,  H03K19/17796

CPC classification number: H03K19/17744 ,  G01R31/31701 ,  H03K19/017581 ,  H03K19/17796

Abstract: Embodiments herein describe connecting an ASIC to another integrated circuit (or die) using inter-die connections. In one embodiment, an ASIC includes a fabric sliver (e.g., a small region of programmable logic circuitry). Inter-die fabric extension connections are used to connect the fabric sliver in the ASIC to fabric (e.g., programmable logic) in the other integrated circuit. These connections effectively extend the fabric in the ASIC to include the fabric in the other integrated circuit. Hardened IP blocks in the ASIC can then use the fabric sliver and the inter-die extension connections to access computer resources in the other integrated circuit.

公开(公告)号：US20240223513A1

公开(公告)日：2024-07-04

申请号：US18089775

申请日：2022-12-28

Applicant: XILINX, INC.

Inventor： Ahmad R. ANSARI ,  John O'DWYER

IPC: H04L49/102 ,  H04L49/109 ,  H04L49/15

CPC classification number: H04L49/102 ,  H04L49/109 ,  H04L49/15

Abstract: Embodiments herein describe an integrated circuit (IC) which includes a global ring that interconnects multiple local rings distributed throughout the IC. In one embodiment, the global ring is connected to the local rings using respective switches. The global ring (and the switches) interconnect the local rings so that a node coupled to one of the local rings can communicate with a node connected to another local ring.

公开(公告)号：US20220224337A1

公开(公告)日：2022-07-14

申请号：US17709164

申请日：2022-03-30

Applicant: XILINX, INC.

Inventor： John Edward MCGRATH ,  Woon WONG ,  John O'DWYER ,  Paul NEWSON ,  Brendan FARLEY

IPC: H03K19/1776

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

公开(公告)号：US20220224338A1

公开(公告)日：2022-07-14

申请号：US17709167

申请日：2022-03-30

Applicant: XILINX, INC.

Inventor： John Edward MCGRATH ,  Woon WONG ,  John O'DWYER ,  Paul NEWSON ,  Brendan FARLEY

IPC: H03K19/1776

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.

公开(公告)号：US20220060189A1

公开(公告)日：2022-02-24

申请号：US17453310

申请日：2021-11-02

Applicant: XILINX, INC.

Inventor： John Edward MCGRATH ,  Woon WONG ,  John O'DWYER ,  Paul NEWSON ,  Brendan FARLEY

IPC: H03K19/1776

Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.