公开(公告)号：US20240184736A1

公开(公告)日：2024-06-06

申请号：US18073327

申请日：2022-12-01

Applicant: XILINX, INC.

Inventor： David P. SCHULTZ ,  Richard W. SWANSON

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F2213/0016

Abstract: An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. A frequency of the interface clock signal is a multiple of a frequency of the logic clock signal.

公开(公告)号：US20240186999A1

公开(公告)日：2024-06-06

申请号：US18073288

申请日：2022-12-01

Applicant: XILINX, INC.

Inventor： David P. SCHULTZ ,  Richard W. SWANSON

IPC: H03K19/0185 ,  H03K19/17736 ,  H03K21/02

CPC classification number: H03K19/01855 ,  H03K19/1774 ,  H03K21/023

Abstract: An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

公开(公告)号：US20240313781A1

公开(公告)日：2024-09-19

申请号：US18123160

申请日：2023-03-17

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE ,  Sagheer AHMAD ,  Trevor J. BAUER ,  Kenneth MA ,  David P. SCHULTZ ,  John O'DWYER ,  Richard W. SWANSON ,  Bhuvanachandran K. NAIR ,  Millind MITTAL

IPC: H03K19/17736 ,  G01R31/317 ,  H03K19/0175 ,  H03K19/17796

CPC classification number: H03K19/17744 ,  G01R31/31701 ,  H03K19/017581 ,  H03K19/17796

Abstract: Embodiments herein describe connecting an ASIC to another integrated circuit (or die) using inter-die connections. In one embodiment, an ASIC includes a fabric sliver (e.g., a small region of programmable logic circuitry). Inter-die fabric extension connections are used to connect the fabric sliver in the ASIC to fabric (e.g., programmable logic) in the other integrated circuit. These connections effectively extend the fabric in the ASIC to include the fabric in the other integrated circuit. Hardened IP blocks in the ASIC can then use the fabric sliver and the inter-die extension connections to access computer resources in the other integrated circuit.