公开(公告)号：US20140252659A1

公开(公告)日：2014-09-11

申请号：US14199640

申请日：2014-03-06

Applicant: XINTEC INC.

Inventor： Yung-Tai TSAI ,  Shu-Ming CHANG ,  Chun-Wei CHANG ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L2224/02371 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00014

Abstract: A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.

Abstract translation: 半导体结构包括晶片，至少一个非金属氧化物层，焊盘，钝化层，隔离层和导电层。 晶片具有连接在第二和第三表面之间的第一表面，第二表面，第三表面，第一阶段差异表面以及连接在第一和第三表面之间的第二阶段差异表面。 非金属氧化物层位于晶片的第一表面上。 垫位于非金属氧化物层上并电连接到晶片。 钝化层位于非金属氧化物层上。 隔离层位于钝化层，非金属氧化物层，晶片的第一，第二和第三表面以及晶片的第一和第二级差分表面上。 导电层位于隔离层上并电接触焊盘。

公开(公告)号：US20150097299A1

公开(公告)日：2015-04-09

申请号：US14504319

申请日：2014-10-01

Applicant: XINTEC INC.

Inventor： Chien-Hui CHEN ,  Tsang-Yu LIU ,  Chun-Wei CHANG ,  Chia-Ming CHENG

IPC: H01L25/065 ,  H01L21/50

CPC classification number: H01L25/0655 ,  H01L21/6835 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided.

Abstract translation: 提供一种形成芯片封装的方法。 提供第一基板。 第二衬底附接在第一衬底上，其中第二衬底具有由划线区域分隔的多个矩形芯片区域。 去除对应于划线区域的第二基板的一部分，以在第一基板上形成多个芯片，其中在相邻芯片之间形成至少一个桥接部分。 还提供了通过该方法形成的芯片封装。

公开(公告)号：US20140312482A1

公开(公告)日：2014-10-23

申请号：US14255872

申请日：2014-04-17

Applicant: XINTEC INC.

Inventor： Chun-Wei CHANG ,  Kuei-Wei CHEN ,  Chia-Ming CHENG ,  Chia-Sheng LIN ,  Chien-Hui CHEN ,  Tsang-Yu LIU

IPC: H01L23/00

CPC classification number: H01L24/26 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/94 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05566 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/03

Abstract: A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

Abstract translation: 提供晶片级的芯片阵列。 晶片级的芯片阵列包括半导体晶片和至少一个延伸线保护。 半导体晶片具有彼此相邻布置的至少两个芯片和载体层。 每个芯片具有上表面和下表面，并且包括至少一个装置。 该装置设置在上表面上，被载体层覆盖。 延伸线保护设置在载体层之下和两个芯片之间。 延长线保护的厚度小于芯片的厚度。 其中延伸线保护件中至少有一条延伸线。 此外，还提供了由晶片级阵列芯片制造的芯片封装及其方法。