公开(公告)号：US20170256496A1

公开(公告)日：2017-09-07

申请号：US15440442

申请日：2017-02-23

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN ,  Chaung-Lin LAI ,  Kuei-Wei CHEN

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/5384 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/05008 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0529 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/13211 ,  H01L2224/13216 ,  H01L2224/13244 ,  H01L2224/13247 ,  H01L2224/13255 ,  H01L2924/146 ,  H01L2924/19102 ,  H01L2924/301 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/06 ,  H01L2924/01074

Abstract: A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. A method of forming the chip package is also provided.

公开(公告)号：US20200098811A1

公开(公告)日：2020-03-26

申请号：US16581594

申请日：2019-09-24

Applicant: XINTEC INC.

Inventor： Kuei-Wei CHEN ,  Chia-Ming CHENG ,  Chia-Sheng LIN

IPC: H01L27/146

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

公开(公告)号：US20140312482A1

公开(公告)日：2014-10-23

申请号：US14255872

申请日：2014-04-17

Applicant: XINTEC INC.

Inventor： Chun-Wei CHANG ,  Kuei-Wei CHEN ,  Chia-Ming CHENG ,  Chia-Sheng LIN ,  Chien-Hui CHEN ,  Tsang-Yu LIU

IPC: H01L23/00

CPC classification number: H01L24/26 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/94 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05566 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/03

Abstract: A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

Abstract translation: 提供晶片级的芯片阵列。 晶片级的芯片阵列包括半导体晶片和至少一个延伸线保护。 半导体晶片具有彼此相邻布置的至少两个芯片和载体层。 每个芯片具有上表面和下表面，并且包括至少一个装置。 该装置设置在上表面上，被载体层覆盖。 延伸线保护设置在载体层之下和两个芯片之间。 延长线保护的厚度小于芯片的厚度。 其中延伸线保护件中至少有一条延伸线。 此外，还提供了由晶片级阵列芯片制造的芯片封装及其方法。

公开(公告)号：US20240178261A1

公开(公告)日：2024-05-30

申请号：US18491713

申请日：2023-10-20

Applicant: XINTEC INC.

Inventor： Kuei-Wei CHEN ,  Chao-Yuan YANG ,  Yueh Hsien LI

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14687 ,  H01L27/1469

Abstract: Chip packages and methods for forming the same are provided. The chip package includes a substrate having a stepped sidewall, a first surface, and a second surface. The first surface and the second surface are opposite each other. The first surface and the second surface adjoin the stepped sidewall. The chip package also includes a capping layer having a first surface and a second surface opposite each other. The first surface of the capping layer faces the second surface of the substrate. The chip package further includes a dam structure and an adhesive layer. The dam structure bonds the capping layer to the substrate, and surrounds a sensing region in the substrate. The adhesive layer surrounds the dam structure and has a concave-tapered sidewall that extends along the outer edge of the dam structure in the direction from the second surface of the substrate to the capping layer.

公开(公告)号：US20220344396A1

公开(公告)日：2022-10-27

申请号：US17861011

申请日：2022-07-08

Applicant: XINTEC INC.

Inventor： Kuei-Wei CHEN ,  Chia-Ming CHENG ,  Chia-Sheng LIN

IPC: H01L27/146

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.