-
公开(公告)号：US07799650B2
公开(公告)日：2010-09-21
申请号：US11835547
申请日：2007-08-08
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/4958 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/7833
摘要： A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure.
摘要翻译： 在半导体材料层上形成半导体器件的方法包括在半导体材料层上形成栅极结构。 该方法还包括形成邻近栅极结构的第一氮化物间隔区，并在半导体材料层中形成源极/漏极延伸部分。 该方法还包括形成覆盖栅极结构和源极/漏极延伸部的氧化物衬垫。 该方法还包括在氧化物衬垫附近形成第二氮化物间隔物。 该方法还包括在半导体材料层中形成源/漏区。 该方法还包括使用对氧化物衬垫有选择性的蚀刻工艺，去除第二氮化物间隔物。 该方法还包括使用对第一氮化物间隔物具有选择性的蚀刻工艺，至少部分地去除氧化物衬垫。 该方法还包括形成覆盖源极/漏极区域和栅极结构的硅化物区域。
-
公开(公告)号：US20090042351A1
公开(公告)日：2009-02-12
申请号：US11835547
申请日：2007-08-08
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/4958 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/7833
摘要： A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure.
摘要翻译： 在半导体材料层上形成半导体器件的方法包括在半导体材料层上形成栅极结构。 该方法还包括形成邻近栅极结构的第一氮化物间隔区，并在半导体材料层中形成源极/漏极延伸部分。 该方法还包括形成覆盖栅极结构和源极/漏极延伸部的氧化物衬垫。 该方法还包括在氧化物衬垫附近形成第二氮化物间隔物。 该方法还包括在半导体材料层中形成源极/漏极区域。 该方法还包括使用对氧化物衬垫有选择性的蚀刻工艺，去除第二氮化物间隔物。 该方法还包括使用对第一氮化物间隔物具有选择性的蚀刻工艺，至少部分地去除氧化物衬垫。 该方法还包括形成覆盖源极/漏极区域和栅极结构的硅化物区域。
-
3.发明授权Method of forming a semiconductor device with multiple tensile stressor layers 有权用多个拉伸应力层形成半导体器件的方法公开(公告)号：US07678698B2
公开(公告)日：2010-03-16
申请号：US11744581
申请日：2007-05-04
IPC分类号： H01L21/44
CPC分类号： H01L29/7843 , H01L21/268 , H01L21/3105 , H01L21/3185 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.
摘要翻译： 半导体器件具有至少两个用UV辐射固化的拉伸应力层。 在第一应力层之后形成第二拉伸应力层。 在一些实例中，拉伸应力层包括氮化硅和氢。 在一些实例中，第二拉伸应力层由于固化而比第一拉伸应力层具有更大的收缩率。 在一种形式中，固化后的第二张应力层比第一拉伸应力层具有更大的拉伸应力。 拉伸应力层用于改善N沟道晶体管中的载流子迁移率，从而提高晶体管性能。 在一种形式中，提供单组上覆的拉伸应力层，每层越来越厚，并且在固化之前具有越来越多的氢。 在其它实施方案中，形成多个重叠的基团，每个基团具有相似的重复深度和氢分布。
-
公开(公告)号：US20080272411A1
公开(公告)日：2008-11-06
申请号：US11744581
申请日：2007-05-04
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/7843 , H01L21/268 , H01L21/3105 , H01L21/3185 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.
摘要翻译： 半导体器件具有至少两个用UV辐射固化的拉伸应力层。 在第一应力层之后形成第二拉伸应力层。 在一些实例中，拉伸应力层包括氮化硅和氢。 在一些实例中，第二拉伸应力层由于固化而比第一拉伸应力层具有更大的收缩率。 在一种形式中，固化后的第二拉伸应力层比第一拉伸应力层具有更大的拉伸应力。 拉伸应力层用于改善N沟道晶体管中的载流子迁移率，从而提高晶体管性能。 在一种形式中，提供单组上覆的拉伸应力层，每层越来越厚，并且在固化之前具有越来越多的氢。 在其它实施方案中，形成多个重叠的基团，每个基团具有相似的重复深度和氢分布。
-
公开(公告)号：US20080261362A1
公开(公告)日：2008-10-23
申请号：US11737496
申请日：2007-04-19
申请人： Da Zhang , Xiangzheng Bo , Venkat R. Kolagunta
发明人： Da Zhang , Xiangzheng Bo , Venkat R. Kolagunta
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.
摘要翻译： 一种用于形成半导体器件的方法包括提供衬底并形成p沟道器件和n沟道器件，每个p沟道器件和n沟道器件包括源极，漏极和栅极， p沟道器件具有第一侧壁间隔物，并且所述n沟道器件具有第二侧壁间隔物。 该方法还包括形成衬套并在衬套上形成拉伸应力层，并从覆盖p沟道器件的区域去除拉伸应力层的一部分。 该方法还包括将拉伸应力层的剩余部分的上覆部分的应力特性转移到n沟道器件的通道。 该方法还包括使用拉伸应力层的剩余部分作为硬掩模，形成邻近p沟道器件的栅极的第一凹槽和第二凹槽。
-
公开(公告)号：US07727870B2
公开(公告)日：2010-06-01
申请号：US11737496
申请日：2007-04-19
申请人： Da Zhang , Xiangzheng Bo , Venkat R. Kolagunta
发明人： Da Zhang , Xiangzheng Bo , Venkat R. Kolagunta
IPC分类号： H01L21/3205
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.
摘要翻译： 一种用于形成半导体器件的方法包括提供衬底并形成p沟道器件和n沟道器件，每个p沟道器件和n沟道器件包括源极，漏极和栅极， p沟道器件具有第一侧壁间隔物，并且所述n沟道器件具有第二侧壁间隔物。 该方法还包括形成衬套并在衬套上形成拉伸应力层，并从覆盖p沟道器件的区域去除拉伸应力层的一部分。 该方法还包括将拉伸应力层的剩余部分的上覆部分的应力特性转移到n沟道器件的通道。 该方法还包括使用拉伸应力层的剩余部分作为硬掩模，形成邻近p沟道器件的栅极的第一凹槽和第二凹槽。
-
公开(公告)号：US20120302022A1
公开(公告)日：2012-11-29
申请号：US13117191
申请日：2011-05-27
申请人： Venkat R. Kolagunta
发明人： Venkat R. Kolagunta
IPC分类号： H01L21/8234
CPC分类号： H01L21/823857 , H01L21/82385
摘要： A method for fabricating at least three different types of devices on a semiconductor substrate comprises forming a first electrode region and a second electrode region for a first semiconductor device at the same time as forming a first electrode region of a asymmetrical semiconductor device, and forming a first electrode region and a second electrode region for a second semiconductor device at the same time as forming a second electrode region of the asymmetrical semiconductor device.
摘要翻译： 一种用于在半导体衬底上制造至少三种不同类型的器件的方法包括在形成第一半导体器件的第一电极区域和第二电极区域的同时形成非对称半导体器件的第一电极区域，并形成 第一电极区域和用于第二半导体器件的第二电极区域，同时形成非对称半导体器件的第二电极区域。
-
8.发明申请PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING INSULATING LAYERS HAVING DIFFERENT STRAINS 有权形成电子装置的方法，包括具有不同应变的绝缘层公开(公告)号：US20110003444A1
公开(公告)日：2011-01-06
申请号：US12883096
申请日：2010-09-15
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/0214 , H01L21/0217 , H01L21/02266 , H01L21/0228 , H01L21/31105 , H01L21/3143 , H01L21/3185 , H01L21/76264 , H01L21/84 , H01L29/78 , H01L29/7843
摘要： An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.
摘要翻译： 电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。 电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。 从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。 在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。 形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。
-
9.发明授权Electronic device including a transistor structure having an active region adjacent to a stressor layer 有权电子器件包括具有与应力层相邻的有源区的晶体管结构公开(公告)号：US07714318B2
公开(公告)日：2010-05-11
申请号：US12180818
申请日：2008-07-28
IPC分类号： H01L29/06
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
摘要翻译： 电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。 例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。 晶体管结构可以包括位于有源区内的沟道区。 有源区域的边缘包括沟道区域和场隔离区域之间的界面。 从顶视图，该层可以包括位于活动区域边缘附近的边缘。 边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。
-
公开(公告)号：US07843011B2
公开(公告)日：2010-11-30
申请号：US11669794
申请日：2007-01-31
IPC分类号： H01L27/092
CPC分类号： H01L27/1203 , H01L21/0214 , H01L21/0217 , H01L21/02266 , H01L21/0228 , H01L21/31105 , H01L21/3143 , H01L21/3185 , H01L21/76264 , H01L21/84 , H01L29/78 , H01L29/7843
摘要： An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.
摘要翻译： 电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。 电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。 从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。 在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。 形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。
-
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.016 秒)
