公开(公告)号：US20100314682A1

公开(公告)日：2010-12-16

申请号：US12661004

申请日：2010-03-05

申请人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

发明人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/762

CPC分类号： H01L29/7397 ,  H01L29/0661 ,  H01L29/66348

摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

摘要翻译： 本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。 半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。 超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。 可以在第一外延层上生长第二外延层。 每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。 每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。

公开(公告)号：US20110140228A1

公开(公告)日：2011-06-16

申请号：US12637988

申请日：2009-12-15

申请人： Xiaobin Wang ,  Anup Bhalla ,  Yeeheng Lee

发明人： Xiaobin Wang ,  Anup Bhalla ,  Yeeheng Lee

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L29/0657 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76227 ,  H01L29/407 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.

摘要翻译： 公开了一种用于产生具有沟槽尺寸TCS和沟槽深度TCD的具有氧化物填充的大深沟槽（OFLDT）部分的半导体器件结构的方法。 体积半导体层（BSL）设置有厚度BSLT> TCD。 一个大的沟槽顶部区域（LTTA）映射到BSL顶部，其几何形状等于OFLDT。 LTTA被划分为散置的，互补的临时区域ITA-A和ITA-B。 通过去除对应于ITA-B的散装半导体材料，在顶部BSL表面上形成了许多深度TCD的临时垂直沟槽。 对应于ITA-A的剩余体积半导体材料被转化为氧化物。 如果在经过转换的ITA-A之间仍然留有剩余空间，则剩余空间被氧化物沉积填满。 重要的是，所有ITA-A和ITA-B的几何形状都应该被简单而小型化，以便于快速有效地进行氧化物转换和氧化物填充。

公开(公告)号：US08390058B2

公开(公告)日：2013-03-05

申请号：US12661004

申请日：2010-03-05

申请人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

发明人： Hamza Yilmaz ,  Madhur Bobde ,  Yeeheng Lee ,  Lingpeng Guan ,  Xiaobin Wang ,  John Chen ,  Anup Bhalla

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7397 ,  H01L29/0661 ,  H01L29/66348

摘要： This invention discloses semiconductor power device disposed on a semiconductor substrate of a first conductivity type. The semiconductor substrate supports an epitaxial layer of a second conductivity type thereon wherein the semiconductor power device is supported on a super-junction structure. The super-junction structure comprises a plurality of trenches opened from a top surface in the epitaxial layer; wherein each of the trenches having trench sidewalls covered with a first epitaxial layer of the first conductivity type to counter charge the epitaxial layer of the second conductivity type. A second epitaxial layer may be grown over the first epitaxial layer. Each of the trenches is filled with a non-doped dielectric material in a remaining trench gap space. Each of the trench sidewalls is opened with a tilted angle to form converging U-shaped trenches.

摘要翻译： 本发明公开了一种设置在第一导电类型的半导体衬底上的半导体功率器件。 半导体衬底在其上支撑第二导电类型的外延层，其中半导体功率器件被支撑在超结结构上。 超结结构包括从外延层中的顶表面开放的多个沟槽; 其中每个沟槽具有覆盖有第一导电类型的第一外延层的沟槽侧壁，以对第二导电类型的外延层进行反电荷充电。 可以在第一外延层上生长第二外延层。 每个沟槽在剩余沟槽间隙空间中填充有非掺杂电介质材料。 每个沟槽侧壁以倾斜角打开以形成会聚的U形沟槽。

公开(公告)号：US08247297B2

公开(公告)日：2012-08-21

申请号：US12637988

申请日：2009-12-15

申请人： Xiaobin Wang ,  Anup Bhalla ,  Yeeheng Lee

发明人： Xiaobin Wang ,  Anup Bhalla ,  Yeeheng Lee

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/0657 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76227 ,  H01L29/407 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.

摘要翻译： 公开了一种用于产生具有沟槽尺寸TCS和沟槽深度TCD的具有氧化物填充的大深沟槽（OFLDT）部分的半导体器件结构的方法。 体积半导体层（BSL）设置有厚度BSLT> TCD。 一个大的沟槽顶部区域（LTTA）映射到BSL顶部，其几何形状等于OFLDT。 LTTA被划分为散置的，互补的临时区域ITA-A和ITA-B。 通过去除对应于ITA-B的散装半导体材料，在顶部BSL表面上形成了许多深度TCD的临时垂直沟槽。 对应于ITA-A的剩余体积半导体材料被转化为氧化物。 如果在经过转换的ITA-A之间仍然留有剩余空间，则剩余空间被氧化物沉积填满。 重要的是，所有ITA-A和ITA-B的几何形状都应该被简单而小型化，以便于快速有效地进行氧化物转换和氧化物填充。

公开(公告)号：US20100291744A1

公开(公告)日：2010-11-18

申请号：US12847863

申请日：2010-07-30

申请人： Yeeheng Lee ,  Hong Chang ,  Tiesheng Li ,  John Chen ,  Anup Bhalla

发明人： Yeeheng Lee ,  Hong Chang ,  Tiesheng Li ,  John Chen ,  Anup Bhalla

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/78

摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

摘要翻译： 沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。 在半导体基板的表面上形成硬掩模。 在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。 这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。 接下来将栅极沟槽掩模施加在硬掩模的顶部上。 栅极沟槽掩模覆盖主体接触沟槽并且在栅极沟槽处具有开口。 栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。 第一种导电材料可以填充栅沟以形成栅极。 第二种导电材料可以填充身体接触沟槽以形成身体接触。

公开(公告)号：US08803251B2

公开(公告)日：2014-08-12

申请号：US13135982

申请日：2011-07-19

申请人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

发明人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

公开(公告)号：US20110147830A1

公开(公告)日：2011-06-23

申请号：US12643837

申请日：2009-12-21

申请人： John Chen ,  Yeeheng Lee ,  Lingpeng Guan ,  Moses Ho ,  Wilson Ma ,  Anup Bhalla ,  Hamza Yilmaz

发明人： John Chen ,  Yeeheng Lee ,  Lingpeng Guan ,  Moses Ho ,  Wilson Ma ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/78 ,  H01L29/7811

摘要： Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns.

摘要翻译： 公开了自对准电荷平衡半导体器件及其形成方法。 在第一导电类型的半导体衬底上形成一个或多个平面栅极。 在与平面栅极自对准的半导体中蚀刻一个或多个深沟槽。 沟槽填充有第二导电类型的半导体材料，使得深沟槽与半导体衬底的相邻区域电荷平衡。该工艺可以形成具有小于12微米的电池间距的自对准电荷平衡装置。

公开(公告)号：US07879676B2

公开(公告)日：2011-02-01

申请号：US12847863

申请日：2010-07-30

申请人： Yeeheng Lee ,  Hong Chang ,  Tiesheng Li ,  John Chen ,  Anup Bhalla

发明人： Yeeheng Lee ,  Hong Chang ,  Tiesheng Li ,  John Chen ,  Anup Bhalla

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/78

摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.

摘要翻译： 沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。 在半导体基板的表面上形成硬掩模。 在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。 这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。 接下来将栅极沟槽掩模施加在硬掩模的顶部上。 栅极沟槽掩模覆盖主体接触沟槽并且在栅极沟槽处具有开口。 栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。 第一种导电材料可以填充栅沟以形成栅极。 第二种导电材料可以填充身体接触沟槽以形成身体接触。

公开(公告)号：US20170125514A9

公开(公告)日：2017-05-04

申请号：US14298922

申请日：2014-06-08

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Yeeheng Lee ,  John Chen ,  Moses Ho

IPC分类号： H01L29/06 ,  H01L21/266 ,  H01L21/324 ,  H01L29/10

CPC分类号： H01L29/0634 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802

摘要： This invention discloses a method for manufacturing a semiconductor power device on a semiconductor substrate supporting a . drift region composed of an epitaxial layer. The method includes a first step of growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; a second step of applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; and a third step of repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers, each of which is implanted with the dopant regions of the alternating conductivity types. Then the manufacturing processes proceed by carrying out a device manufacturing process on a top side of the epitaxial layer on top of the dopant regions of the alternating conductivity types with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.

公开(公告)号：US20150115333A1

公开(公告)日：2015-04-30

申请号：US14062868

申请日：2013-10-24

申请人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Wilson Ma ,  Lingpeng Guan ,  Yeeheng Lee ,  John Chen

发明人： Madhur Bobde ,  Anup Bhalla ,  Hamza Yilmaz ,  Wilson Ma ,  Lingpeng Guan ,  Yeeheng Lee ,  John Chen

IPC分类号： H01L29/10 ,  H01L29/808 ,  H01L27/06

CPC分类号： H01L29/1058 ,  H01L27/0727 ,  H01L29/0634 ,  H01L29/808 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： This invention discloses configurations and methods to manufacture lateral power device including a super-junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.

摘要翻译： 本发明公开了制造横向功率器件的结构和方法，该器件包括在漏极和栅极之间形成的具有雪崩钳位二极管的超结结构。 横向超结结构降低了导通电阻，而结构增强（包括雪崩钳位二极管和N缓冲区）增加了衬底和漏极之间的击穿电压，并改善了非钳位感应开关（UIS）性能。