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公开(公告)号：US10367666B2
公开(公告)日：2019-07-30
申请号：US15471364
申请日：2017-03-28
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Yohan Frans , Geoffrey Zhang
Abstract: A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.
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公开(公告)号：US20160352557A1
公开(公告)日：2016-12-01
申请号：US14723171
申请日：2015-05-27
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Kun-Yung Chang , Toan Pham , Zhaoyin D. Wu
CPC classification number: H04L27/3809 , H04L25/03057 , H04L25/03885
Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.
Abstract translation: 接收机一般涉及信道适配。 在该接收机中，第一信号处理块耦合到通信信道。 第一信号处理块包括：AGC块和CTLE块，用于接收用于提供模拟信号的调制信号; 用于将模拟信号转换为数字样本的ADC; 以及用于均衡数字样本以提供均衡样本的FFE块。 第二信号处理块包括：DFE块，用于接收用于提供重新均衡的采样的采样的均衡; 以及耦合到DFE块的限幅器，用于对重新平衡的样本进行切片。 接收机适配块耦合到第一信号处理块和第二信号处理块。 接收器适配块被配置用于提供AGC适配，CTLE适配和对通信信道的限幅器适配。
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公开(公告)号：US10404445B1
公开(公告)日：2019-09-03
申请号：US16026967
申请日：2018-07-03
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Jinyung NamKoong , Winson Lin , Yohan Frans , Geoffrey Zhang
Abstract: A receiver circuit for receiving data is described. The receiver circuit comprises a phase detector configured to receive an input data signal; a frequency path circuit configured to receive an output of the phase detector; and a false lock detection circuit configured to receive the output of the phase detector and an output of the frequency path circuit; wherein the false lock detection circuit detects a false lock of the receiver circuit to the input data signal based upon an output of the phase detector and provides a frequency offset to the frequency path circuit. A method of receiving data is also described.
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公开(公告)号：US10291239B1
公开(公告)日：2019-05-14
申请号：US16000698
申请日：2018-06-05
Applicant: Xilinx, Inc.
Inventor： Zhaoyin D. Wu , Winson Lin , Parag Upadhyaya , Geoffrey Zhang , Kun-Yung Chang
Abstract: An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.
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5.发明授权Circuits for and methods of robust adaptation of a continuous time linear equalizer circuit 有权电路和连续时间线性均衡电路的鲁棒适应方法公开(公告)号：US09461851B1
公开(公告)日：2016-10-04
申请号：US14885666
申请日：2015-10-16
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang
CPC classification number: H04L27/01 , H04L25/0212 , H04L25/03019 , H04L25/03057 , H04L25/03885
Abstract: A circuit for enabling an adaptation of an equalization circuit is described. The circuit comprises a continuous time linear equalizer configured to receive an input data signal and generate an equalized input data signal; a decision circuit configured to receive the equalized input data signal, wherein the decision circuit generates an estimate of the input data signal; channel estimation circuit configured to receive the estimate of the input data signal and an error signal to generate an impulse response estimate of an equivalent channel; a frequency response computation circuit configured to receive the impulse response estimate of the equivalent channel and generate a channel frequency response; and a continuous time linear equalizer control circuit configured to receive the channel frequency response and to generate a CTLE adaptation signal for controlling the continuous time linear equalizer.
Abstract translation: 描述了一种用于实现均衡电路的适配的电路。 电路包括连续时间线性均衡器，被配置为接收输入数据信号并产生均衡的输入数据信号; 判定电路，被配置为接收所述均衡输入数据信号，其中所述判定电路生成所述输入数据信号的估计; 信道估计电路，被配置为接收输入数据信号的估计和误差信号，以产生等效信道的脉冲响应估计; 频率响应计算电路，被配置为接收等效信道的脉冲响应估计并产生信道频率响应; 以及连续时间线性均衡器控制电路，被配置为接收信道频率响应并产生用于控制连续时间线性均衡器的CTLE自适应信号。
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Patent Agency Ranking
6.发明授权Circuits for and methods of filtering inter-symbol interference for SerDes applications 有权用于SerDes应用的滤波符号间干扰的电路和方法公开(公告)号：US09313054B1
公开(公告)日：2016-04-12
申请号：US14617015
申请日：2015-02-09
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Hongtao Zhang , Geoffrey Zhang , Kun-Yung Chang
CPC classification number: H04L25/03019 , H04L2025/03484
Abstract: A circuit for filtering inter-symbol interference in an integrated circuit is described. The circuit comprises a first stage coupled to receive digital samples of an input signal. The first stage generates first decision outputs based upon the digital samples. A second stage is coupled to receive the digital samples of the input signal. The second stage comprises a filter receiving the first decision outputs and generating second decision outputs based upon the digital samples of the input signal and detected inter-symbol interference associated with the first decision outputs. A method of filtering inter-symbol interference in an integrated circuit is also described.
Abstract translation: 描述用于滤波集成电路中符号间干扰的电路。 电路包括耦合以接收输入信号的数字样本的第一级。 第一阶段基于数字样本产生第一决策输出。 第二级被耦合以接收输入信号的数字样本。 第二级包括接收第一判定输出并基于输入信号的数字样本和检测到的与第一判定输出相关联的符号间干扰的第二判定输出的滤波器。 还描述了一种对集成电路中符号间干扰进行滤波的方法。
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公开(公告)号：US09882795B1
公开(公告)日：2018-01-30
申请号：US14689327
申请日：2015-04-17
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Geoffrey Zhang , Yu Xu , Patrick Satarzadeh , Zhaoyin D. Wu
CPC classification number: H04L43/0811 , H04L7/0087 , H04L25/03057
Abstract: In an example, an apparatus for detecting signal loss on a serial communication channel coupled to a receiver includes an input, a detector, and an output circuit. The input is configured to receive decisions generated by sampling the serial communication channel using multiplexed decision paths in a decision feedback equalizer (DFE). The detector is coupled to the input and configured to monitor the decisions for at least one pattern generated by the multiplexed decision paths in response to absence of a serial data signal on the serial communication channel. The output circuit is coupled to the detector and configured to assert loss-of-signal in response detection of the at least one pattern by the detector.
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公开(公告)号：US09800438B1
公开(公告)日：2017-10-24
申请号：US15333505
申请日：2016-10-25
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Zhaoyin D. Wu , Christopher J. Borrelli , Geoffrey Zhang
CPC classification number: H04L25/03885 , G01R31/02 , G01R31/44 , H04L7/0025 , H04L7/0087 , H04L25/03273
Abstract: An example method of performing an eye-scan in a receiver includes: generating digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference clock based on a phase interpolator (PI) code; equalizing the digital samples based on first equalization parameters of a plurality of equalization parameters of the receiver; adapting the plurality of equalization parameters and performing clock recovery based on the digital samples to generate the PI code; and performing a plurality of cycles of locking the plurality of equalization parameters, suspending phase detection in the clock recovery, offsetting the PI code, collecting an output of the receiver, resuming the phase detection in the clock recovery, and unlocking the equalization parameters to perform the eye scan.
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公开(公告)号：US09654327B2
公开(公告)日：2017-05-16
申请号：US14723171
申请日：2015-05-27
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Geoffrey Zhang , Hongtao Zhang , Kun-Yung Chang , Toan Pham , Zhaoyin D. Wu
CPC classification number: H04L27/3809 , H04L25/03057 , H04L25/03885
Abstract: A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.
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10.发明授权公开(公告)号：US09379920B1
公开(公告)日：2016-06-28
申请号：US14707919
申请日：2015-05-08
Applicant: Xilinx, Inc.
Inventor： Yu Liao , Hongtao Zhang , Kun-Yung Chang , Geoffrey Zhang
CPC classification number: H04L25/03057 , H04L25/03 , H04L25/03146 , H04L25/03878 , H04L25/03885 , H04L27/01 , H04L2025/0349 , H04L2025/03503
Abstract: In a receiver, a decision feedback equalizer (“DFE”) receives an analog input signal. The DFE includes a subtraction block for subtracting weighted postcursor decisions from an analog input signal to provide an analog output signal. A postcursor decision block coupled to the DFE compares the analog output signal against positive and negative values of a postcursor coefficient to provide first and second possible decisions for selecting a current postcursor-based decision therebetween responsive to a previous postcursor-based decision. A precursor cancellation block receives the analog output signal, the previous postcursor-based decision and the current postcursor-based decision for providing a digital output signal for a previous sample of the analog input signal.
Abstract translation: 在接收机中，判决反馈均衡器（“DFE”）接收模拟输入信号。 DFE包括用于从模拟输入信号减去加权后移判定的减法模块以提供模拟输出信号。 耦合到DFE的后端判定块将模拟输出信号与后移系数的正值和负值进行比较，以响应于先前的基于后期的判定来提供用于选择当前基于后台的判定的第一和第二可能决定。 前体消除块接收模拟输出信号，先前的基于后期的判定和当前的基于前后的判定，用于为模拟输入信号的先前样本提供数字输出信号。
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