公开(公告)号：US11923857B1

公开(公告)日：2024-03-05

申请号：US18102066

申请日：2023-01-26

申请人： XILINX, INC.

发明人： Hongtao Zhang ,  Ankur Jain ,  Yanfei Chen ,  Ronan Sean Casey ,  Winson Lin ,  Hsung Jai Im

IPC分类号： H03L7/08 ,  H03L7/099 ,  H03M1/82

CPC分类号： H03L7/0802 ,  H03L7/0991 ,  H03M1/82

摘要： Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.

公开(公告)号：US10985764B1

公开(公告)日：2021-04-20

申请号：US16918854

申请日：2020-07-01

申请人： XILINX, INC.

发明人： Winson Lin ,  Jin Namkoong ,  Hongtao Zhang

IPC分类号： H04L7/00 ,  H04L7/033 ,  H04L25/03 ,  H03L7/087 ,  H03L7/08

摘要： An example method of clock and data recovery (CDR) includes adding a pre-defined offset to an output of a phase detector (PD) of a CDR circuit, and loading an accumulator of a frequency loop of the CDR circuit with a pre-defined load value. The method further includes detecting the phase of an incoming signal using a PD, and determining that the CDR has locked onto a real lock point. In some examples, the method further includes determining that the CDR has locked on a real lock point, and, in response to the determination, modifying the pre-defined offset to equal zero.

公开(公告)号：US10367666B2

公开(公告)日：2019-07-30

申请号：US15471364

申请日：2017-03-28

申请人： Xilinx, Inc.

发明人： Hongtao Zhang ,  Yohan Frans ,  Geoffrey Zhang

IPC分类号： H04B1/06 ,  H04L27/01 ,  H03M1/18 ,  H04L25/06 ,  H03M1/36

摘要： A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.

公开(公告)号：US20160352557A1

公开(公告)日：2016-12-01

申请号：US14723171

申请日：2015-05-27

申请人： Xilinx, Inc.

发明人： Yu Liao ,  Geoffrey Zhang ,  Hongtao Zhang ,  Kun-Yung Chang ,  Toan Pham ,  Zhaoyin D. Wu

IPC分类号： H04L27/38 ,  H04L25/03

CPC分类号： H04L27/3809 ,  H04L25/03057 ,  H04L25/03885

摘要： A receiver relates generally to channel adaptation. In this receiver, a first signal processing block is coupled to a communications channel. The first signal processing block includes: an AGC block and a CTLE block for receiving a modulated signal for providing an analog signal; an ADC for converting the analog signal to digital samples; and an FFE block for equalizing the digital samples to provide equalized samples. A second signal processing block includes: a DFE block for receiving the equalized sampled for providing re-equalized samples; and a slicer coupled to the DFE block for slicing the re-equalized samples. A receiver adaptation block is coupled to the first signal processing block and the second signal processing block. The receiver adaptation block is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel.

摘要翻译： 接收机一般涉及信道适配。 在该接收机中，第一信号处理块耦合到通信信道。 第一信号处理块包括：AGC块和CTLE块，用于接收用于提供模拟信号的调制信号; 用于将模拟信号转换为数字样本的ADC; 以及用于均衡数字样本以提供均衡样本的FFE块。 第二信号处理块包括：DFE块，用于接收用于提供重新均衡的采样的采样的均衡; 以及耦合到DFE块的限幅器，用于对重新平衡的样本进行切片。 接收机适配块耦合到第一信号处理块和第二信号处理块。 接收器适配块被配置用于提供AGC适配，CTLE适配和对通信信道的限幅器适配。

公开(公告)号：US11876523B1

公开(公告)日：2024-01-16

申请号：US18079649

申请日：2022-12-12

申请人： XILINX, INC.

发明人： Hongtao Zhang ,  Ankur Jain ,  Hsung Jai Im

IPC分类号： H03L7/093 ,  H03L7/081 ,  G04F10/00 ,  H03M1/08 ,  H03L7/099

CPC分类号： H03L7/093 ,  G04F10/005 ,  H03L7/081 ,  H03L7/099 ,  H03M1/0854

摘要： Embodiments herein describe normalizing an output of a TDC in a DPLL to a resolution of the TDC. A DTC can delay a reference clock which is then input into the TDC. The TDC outputs a digital code indicating a time difference between the delayed reference clock output by the DTC and a clock generated by a DCO in the DPLL. This digital code is normalized to a resolution of the TDC and the result is filtered by a DLF.

公开(公告)号：US11245554B1

公开(公告)日：2022-02-08

申请号：US16903377

申请日：2020-06-17

申请人： XILINX, INC.

发明人： Hongtao Zhang ,  Winson Lin ,  Arianne Roldan ,  Yohan Frans ,  Geoff Zhang

IPC分类号： H04L25/03 ,  H03L7/089 ,  H04L27/01

摘要： An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

公开(公告)号：US10404445B1

公开(公告)日：2019-09-03

申请号：US16026967

申请日：2018-07-03

申请人： Xilinx, Inc.

发明人： Hongtao Zhang ,  Jinyung NamKoong ,  Winson Lin ,  Yohan Frans ,  Geoffrey Zhang

IPC分类号： H03D3/24 ,  H04L7/00 ,  H04L7/033 ,  H03L7/081

摘要： A receiver circuit for receiving data is described. The receiver circuit comprises a phase detector configured to receive an input data signal; a frequency path circuit configured to receive an output of the phase detector; and a false lock detection circuit configured to receive the output of the phase detector and an output of the frequency path circuit; wherein the false lock detection circuit detects a false lock of the receiver circuit to the input data signal based upon an output of the phase detector and provides a frequency offset to the frequency path circuit. A method of receiving data is also described.

公开(公告)号：US09313054B1

公开(公告)日：2016-04-12

申请号：US14617015

申请日：2015-02-09

申请人： Xilinx, Inc.

发明人： Yu Liao ,  Hongtao Zhang ,  Geoffrey Zhang ,  Kun-Yung Chang

IPC分类号： H03H7/30 ,  H04L25/03

CPC分类号： H04L25/03019 ,  H04L2025/03484

摘要： A circuit for filtering inter-symbol interference in an integrated circuit is described. The circuit comprises a first stage coupled to receive digital samples of an input signal. The first stage generates first decision outputs based upon the digital samples. A second stage is coupled to receive the digital samples of the input signal. The second stage comprises a filter receiving the first decision outputs and generating second decision outputs based upon the digital samples of the input signal and detected inter-symbol interference associated with the first decision outputs. A method of filtering inter-symbol interference in an integrated circuit is also described.

摘要翻译： 描述用于滤波集成电路中符号间干扰的电路。 电路包括耦合以接收输入信号的数字样本的第一级。 第一阶段基于数字样本产生第一决策输出。 第二级被耦合以接收输入信号的数字样本。 第二级包括接收第一判定输出并基于输入信号的数字样本和检测到的与第一判定输出相关联的符号间干扰的第二判定输出的滤波器。 还描述了一种对集成电路中符号间干扰进行滤波的方法。

公开(公告)号：US11038768B1

公开(公告)日：2021-06-15

申请号：US15267002

申请日：2016-09-15

申请人： Xilinx, Inc.

发明人： Ivan O. Madrigal ,  Michael O. Jenkins ,  Hong S. Ahn ,  Murtuza Z. Cutleriwala ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans ,  Geoffrey Zhang ,  Hongtao Zhang

IPC分类号： H04L25/03 ,  H04L12/24 ,  G06F30/331

摘要： A method relates generally to comparison of a communications system modelled with a behavioral model and implemented with a circuit realization. In this method, operation of the communications system is simulated with the behavioral model on a computing device to obtain a first pulse response. The simulating includes first equalizing first data with a first equalizer of the behavioral model to obtain the first pulse response. The circuit realization is operated to obtain a second pulse response. The operating includes: second equalizing second data corresponding to the first data with a second equalizer of the circuit realization to obtain the second pulse response. The second pulse response from the circuit realization is loaded to memory of the computing device. The first pulse is loaded to the memory of the computing device. The first pulse response and the second pulse response are compared with one another by the computing device.

公开(公告)号：US10348290B1

公开(公告)日：2019-07-09

申请号：US15472080

申请日：2017-03-28

申请人： Xilinx, Inc.

发明人： Hongtao Zhang ,  Yohan Frans

IPC分类号： H04B1/04 ,  H03K17/14 ,  H03K19/177

摘要： A transmitter includes a predriver circuit configured to perform a first equalization process to compensate jitter caused by the predriver circuit. The predriver circuit includes a first path having a first driving strength and configured to generate a first path output signal by applying a first delay to a predriver input signal. The predriver circuit includes a second path having a second driving strength less than the first driving strength and configured to generate a second path output signal by applying a second delay to the predriver input signal. A summing node is configured to combine the first path output signal and the second path output signal to provide a summing node output signal. A driver circuit coupled to the predriver circuit is configured to generate a driver output signal based on the summing node output signal and drive the driver output signal to a receiver through a channel.