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    Multi-Level Contact to a 3D Memory Array and Method of Making
    1.
    发明申请
    Multi-Level Contact to a 3D Memory Array and Method of Making 有权
    与3D内存阵列的多层接触及其制作方法

    公开(公告)号：US20130313627A1

    公开(公告)日：2013-11-28

    申请号：US13478483

    申请日：2012-05-23

    申请人： Yao-Sheng Lee ,  Zhen Chen ,  Syo Fukata

    发明人： Yao-Sheng Lee ,  Zhen Chen ,  Syo Fukata

    IPC分类号： H01L21/768 ,  H01L29/792 ,  H01L23/48

    CPC分类号： H01L27/11578 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/481 ,  H01L27/10802 ,  H01L27/11 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.

    摘要翻译： 制作多层次联系的方法。 该方法包括提供包括至少一个设备区域和至少一个接触区域的进程内多电平设备。 接触区域包括以台阶图案配置的多个导电层。 该方法还包括在多个导电层上形成共形蚀刻停止层，在蚀刻停止层上形成第一电绝缘层，在第一电绝缘层上形成共形牺牲层，并形成第二电绝缘层 牺牲层。 该方法还包括通过蚀刻停止层，接触区域中的第一电绝缘层，牺牲层和第二电绝缘层蚀刻到多个导电层的多个接触开口。

    Multi-level contact to a 3D memory array and method of making
    2.
    发明授权
    Multi-level contact to a 3D memory array and method of making 有权
    与3D内存阵列的多层次接触和制作方法

    公开(公告)号：US08828884B2

    公开(公告)日：2014-09-09

    申请号：US13478483

    申请日：2012-05-23

    申请人： Yao-Sheng Lee ,  Zhen Chen ,  Syo Fukata

    发明人： Yao-Sheng Lee ,  Zhen Chen ,  Syo Fukata

    IPC分类号： H01L21/467

    CPC分类号： H01L27/11578 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/481 ,  H01L27/10802 ,  H01L27/11 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.

    摘要翻译： 制作多层次联系的方法。 该方法包括提供包括至少一个设备区域和至少一个接触区域的进程内多电平设备。 接触区域包括以台阶图案配置的多个导电层。 该方法还包括在多个导电层上形成共形蚀刻停止层，在蚀刻停止层上形成第一电绝缘层，在第一电绝缘层上形成共形牺牲层，并形成第二电绝缘层 牺牲层。 该方法还包括通过蚀刻停止层，接触区域中的第一电绝缘层，牺牲层和第二电绝缘层蚀刻到多个导电层的多个接触开口。

    Ultrahigh density vertical NAND memory device and method of making thereof
    5.
    发明授权
    Ultrahigh density vertical NAND memory device and method of making thereof 有权
    超高密度垂直NAND存储器件及其制造方法

    公开(公告)号：US08187936B2

    公开(公告)日：2012-05-29

    申请号：US12827947

    申请日：2010-06-30

    申请人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

    发明人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

    摘要： A method of making a monolithic three dimensional NAND string. The method includes forming a stack of alternating layers of a first material and a second material over a substrate. The first material includes a conductive or semiconductor control gate material and the second material includes an insulating material. The method also includes etching the stack to form at least one opening in the stack, selectively etching the first material to form first recesses in the first material and forming a blocking dielectric in the first recesses. The method also includes forming a plurality of discrete charge storage segments separated from each other in the first recesses over the blocking dielectric, forming a tunnel dielectric over a side wall of the discrete charge storage segments exposed in the at least one opening and forming a semiconductor channel in the at least one opening.

    摘要翻译： 制造单片三维NAND串的方法。 该方法包括在衬底上形成第一材料和第二材料的交替层的叠层。 第一材料包括导电或半导体控制栅极材料，第二材料包括绝缘材料。 该方法还包括蚀刻堆叠以在堆叠中形成至少一个开口，选择性地蚀刻第一材料以在第一材料中形成第一凹槽并在第一凹槽中形成阻挡电介质。 该方法还包括在隔离电介质上的第一凹槽中形成彼此分开的多个离散的电荷存储段，在暴露在至少一个开口中的离散电荷存储段的侧壁上形成隧道电介质，并形成半导体 通道在至少一个开口中。

    Method of making a three-dimensional memory array with etch stop
    6.
    发明授权
    Method of making a three-dimensional memory array with etch stop 有权
    制造具有蚀刻停止的三维存储阵列的方法

    公开(公告)号：US08614126B1

    公开(公告)日：2013-12-24

    申请号：US13586413

    申请日：2012-08-15

    申请人： Yao-Sheng Lee ,  Johann Alsmeier

    发明人： Yao-Sheng Lee ,  Johann Alsmeier

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/11551 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

    摘要： A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The device also includes an etch stop layer located between the substrate and the plurality of control gate electrodes.

    摘要翻译： 一种包括衬底和半导体沟道的三维存储器件。 半导体通道的至少一个端部基本上垂直于衬底的主表面延伸。 该器件还包括位于半导体通道附近的至少一个电荷存储区域以及具有基本上平行于衬底的主表面延伸的条带形状的多个控制栅极电极。 多个控制栅电极至少包括位于第一器件级的第一控制栅电极和位于位于衬底的主表面上方且低于第一器件电平的第二器件电平的第二控制栅电极。 该器件还包括位于衬底和多个控制栅电极之间的蚀刻停止层。

    Method for making memory elements
    8.
    发明申请
    Method for making memory elements 审中-公开
    制作记忆元素的方法

    公开(公告)号：US20050040136A1

    公开(公告)日：2005-02-24

    申请号：US10895277

    申请日：2004-07-20

    申请人： Yao-Sheng Lee ,  Mike DeVre

    发明人： Yao-Sheng Lee ,  Mike DeVre

    IPC分类号： H01L45/00 ,  B44C1/22

    CPC分类号： H01L45/06 ,  H01L45/144 ,  H01L45/1675

    摘要： The present invention provides an improved method for forming a memory element having a chalcogenide layer such as Ge2Sb2Te5. A substrate having a dielectric etch stop layer, a chalcogenide layer, an anti-reflective layer and a mask layer is placed in a vacuum chamber having a high density plasma source. At least one chlorine containing gas, such as a mixture of BCl3 and Cl2, is introduced into the vacuum chamber for etching the chalcogenide layer and the anti-reflective layer to the dielectric etch stop layer. The etch process is discontinued based on an endpoint detection system. Upon completion of the etch process, the substrate is removed from the vacuum chamber and the mask layer is stripped from the substrate.

    摘要翻译： 本发明提供了一种用于形成具有诸如Ge 2 Sb 2 Te 5的硫族化物层的存储元件的改进方法。 将具有电介质蚀刻停止层，硫族化物层，抗反射层和掩模层的衬底放置在具有高密度等离子体源的真空室中。 将至少一种含氯气体，例如BCl 3和Cl 2的混合物引入真空室中，用于将硫族化物层和抗反射层蚀刻到电介质蚀刻停止层。 基于端点检测系统停止蚀刻工艺。 在完成蚀刻工艺后，将基板从真空室中取出，掩模层从基板上剥离。

    High aspect ratio memory hole channel contact formation
    9.
    发明授权
    High aspect ratio memory hole channel contact formation 有权
    高纵横比记忆孔通道接触形成

    公开(公告)号：US09460931B2

    公开(公告)日：2016-10-04

    申请号：US14225176

    申请日：2014-03-25

    申请人： Jayavel Pachamuthu ,  Johann Alsmeier ,  Raghuveer S. Makala ,  Yao-Sheng Lee

    发明人： Jayavel Pachamuthu ,  Johann Alsmeier ,  Raghuveer S. Makala ,  Yao-Sheng Lee

    IPC分类号： H01L21/28 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L29/788

    CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： A memory device and a method of fabricating a memory device that includes forming a protrusion over a substrate, an etch stop layer over the protrusion, and a stack of alternating material layers over the etch stop layer. The method further includes etching the stack to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer, etching the etch stop layer to provide a void area between the protrusion and a bottom of the memory opening, where the void area has a second width dimension that is larger than the first width dimension, forming a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion, etching the memory film to expose the protrusion, and forming a semiconductor channel in the memory opening that is electrically coupled to the protrusion.

    摘要翻译： 一种存储器件和一种制造存储器件的方法，所述存储器件包括在衬底上形成突起，在所述突起上方形成蚀刻停止层，以及在所述蚀刻停止层上方的交替材料层堆叠。 所述方法还包括将所述叠层蚀刻到所述蚀刻停止层以形成具有靠近所述蚀刻停止层的第一宽度尺寸的存储器开口，蚀刻所述蚀刻停止层以在所述突起与所述存储器开口的底部之间提供空隙区域， 其中所述空隙区域具有大于所述第一宽度尺寸的第二宽度尺寸，在所述存储器开口的侧壁上并且在所述突起的顶表面上方的所述空隙区域内形成记忆膜，蚀刻所述存储膜以暴露所述突起 并且在与所述突起电耦合的所述存储器开口中形成半导体通道。

    Method of pattern etching a dielectric film while removing a mask layer
    10.
    发明授权
    Method of pattern etching a dielectric film while removing a mask layer 有权
    在去除掩模层的同时刻蚀电介质膜的方法

    公开(公告)号：US08252192B2

    公开(公告)日：2012-08-28

    申请号：US12411565

    申请日：2009-03-26

    申请人： Yao-Sheng Lee ,  Vaidyanathan Balasubramaniam ,  Masaru Nishino ,  Kelvin Zin

    发明人： Yao-Sheng Lee ,  Vaidyanathan Balasubramaniam ,  Masaru Nishino ,  Kelvin Zin

    IPC分类号： C03C15/00 ,  C03C25/68 ,  C23F1/00

    CPC分类号： H01L21/67069 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816

    摘要： A method of pattern etching a thin film on a substrate is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a dielectric layer formed on the substrate and a mask layer formed above the dielectric layer. A pattern is created in the mask layer, and the pattern is transferred from the mask layer to the dielectric layer by performing a plasma etching process. While transferring the pattern to the dielectric layer, the mask layer is substantially removed using the plasma etching process. The plasma etching process can use a process gas comprising a first gaseous component that etches the dielectric layer at a greater rate than the mask layer, and a second gaseous component that etches the dielectric layer at a lesser rate than the mask layer.

    摘要翻译： 描述了在衬底上图案蚀刻薄膜的方法。 该方法包括在衬底上制备膜堆叠，其中膜堆叠包括形成在衬底上的电介质层和形成在电介质层上方的掩模层。 在掩模层中形成图案，通过进行等离子体蚀刻工艺，将图案从掩模层转印到电介质层。 当将图案转印到电介质层时，使用等离子体蚀刻工艺基本上去除掩模层。 等离子体蚀刻工艺可以使用包括以比掩模层更高的速率蚀刻电介质层的第一气态组分的工艺气体和以比掩模层更低的速率蚀刻介电层的第二气体组分。