公开(公告)号：US06476524B1

公开(公告)日：2002-11-05

申请号：US09601900

申请日：2000-09-21

申请人： Yasuhiro Miyamoto ,  Kazuhiro Maekawa ,  Takato Doi ,  Masaki Hisatsune

发明人： Yasuhiro Miyamoto ,  Kazuhiro Maekawa ,  Takato Doi ,  Masaki Hisatsune

IPC分类号： H02K4103

CPC分类号： H02K41/031 ,  H02K1/148 ,  H02K11/00

摘要： A moving-coil linear motor free of cogging. The motor has a rotor (3) including separated block cores (31, 32 and 33), each of which has a length equivalent to eight times the magnet pitch (Pm) and includes nine teeth (4) along the length. The block cores are arranged in line and separated by gaps equivalent to ⅔ of the magnet pitch. The first block (31) is divided into three groups of teeth (4) with armature coils (5) to form U-, V- and W-phases. Similarly, the second block (32) is grouped to form V-, W- and U-phases, and the third block (33) is grouped to form W-, U- and V-phases. The armature coils (5) are formed to differ in phase by 120 degrees from one another in order to zero the sum of the cogging caused by the blocks.

摘要翻译： 动圈式线性电机无齿槽。 电动机具有转子（3），该转子包括分离的块芯（31,32和33），每个转子具有相当于磁体间距（Pm）的八倍的长度，并且包括沿该长度的九个齿（4）。 块芯线排成一行，并相当于磁体间距的2/3的间隙。 第一块（31）被分成具有电枢线圈（5）的三组齿（4），以形成U相，V相和W相。 类似地，第二块（32）被分组以形成V-，W-和U-相，并且第三块（33）被分组以形成W-，U-和V-相位。 电枢线圈（5）形成为彼此相位相差120度，以使由块产生的齿槽的总和为零。

公开(公告)号：US06407471B1

公开(公告)日：2002-06-18

申请号：US09597552

申请日：2000-06-19

申请人： Yasuhiro Miyamoto ,  Masaki Hisatsune ,  Kazuhiro Maekawa ,  Takato Doi ,  Masahiko Tanabe

发明人： Yasuhiro Miyamoto ,  Masaki Hisatsune ,  Kazuhiro Maekawa ,  Takato Doi ,  Masahiko Tanabe

IPC分类号： H02K4100

CPC分类号： H02K41/03 ,  H02K1/14 ,  Y10T29/49009

摘要： The invention relates to a linear motor which is provided with a row of permanent magnets 6a, 6b, 6c, . . . for a field system, and an armature 2 facing the same via a magnetized space in an orthogonal direction thereto, wherein the armature core 3 has a winding accommodation groove 3a formed at both sides of armature iron plates produced by punching out oriented electromagnetic steel plate so as to become rectangular, and convex and concave engagement portions 3b and 3c, the armature iron plates are laminated to constitute one core block, and at the same time, the lengthwise direction, orthogonal to the permanent magnet row, in the respective core blocks is made the same as the rolling direction of electromagnetic steel plates. Thereby, since the magnetic flux of the armature winding 4 flows along the rolling direction of the core blocks, the magnetic flux density can be increased, and the peak thrust can be also increased.

摘要翻译： 本发明涉及一种具有一排永磁体6a，6b，6c，...的线性电动机。 。 。 并且电枢2经由磁化空间与其正交的方向对置，其中电枢铁心3具有形成在通过冲压取向电磁钢板制造的电枢铁板的两侧的绕组容纳槽3a， 为了形成矩形和凸凹接合部分3b和3c，电枢铁板被层叠以构成一个芯块，同时在各个芯块中与永磁体列垂直的纵向是 与电磁钢板的轧制方向相同。 因此，由于电枢绕组4的磁通量沿芯块的轧制方向流动，所以可以提高磁通密度，并且也可以提高峰值推力。

公开(公告)号：US08547773B2

公开(公告)日：2013-10-01

申请号：US11477714

申请日：2006-06-30

申请人： Takayuki Saiki ,  Satoru Ito ,  Masahiko Moriguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Kazuhiro Maekawa

发明人： Takayuki Saiki ,  Satoru Ito ,  Masahiko Moriguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Kazuhiro Maekawa

IPC分类号： G11C8/00

CPC分类号： G09G3/3674 ,  G09G3/3685

摘要： An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TC1 and TC2, each of the control transistors being provided corresponding to each output line of the data driver block and controlled by using a common control signal, and a pad arrangement region in which data driver pads P1 and P2 for electrically connecting the data lines and the output lines QL1 and QL2 of the data driver block are disposed. The control transistors TC1 and TC2 are disposed in the pad arrangement region.

摘要翻译： 集成电路装置包括用于驱动数据线的至少一个数据驱动器块，多个控制晶体管TC1和TC2，每个控制晶体管对应于数据驱动器模块的每个输出线提供，并通过使用公共控制信号 以及其中设置用于电连接数据线和数据驱动器块的输出线QL1和QL2的数据驱动器焊盘P1和P2的焊盘布置区域。 控制晶体管TC1和TC2设置在焊盘布置区域中。

公开(公告)号：US07782694B2

公开(公告)日：2010-08-24

申请号：US11477716

申请日：2006-06-30

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

IPC分类号： G11C7/00

CPC分类号： G09G3/20 ,  G09G2310/027 ,  G09G2360/18

摘要： An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.

摘要翻译： 集成电路装置包括显示存储器和数据读取控制电路。 数据读取控制电路控制数据读取，使得通过在显示面板的一个水平扫描周期（N是大于1的整数）中的N次读取来读出与多条信号线相对应的像素的数据。 显示存储器包括分别与多个位线连接的多个读出放大器单元。 分别与字线延伸的第一方向（字线方向）相邻的L个存储单元的位线分别连接的L个读出放大器单元（L是大于1的整数）沿着位线延伸的第二个方向（位线方向） 。

公开(公告)号：US20100157182A1

公开(公告)日：2010-06-24

申请号：US12656129

申请日：2010-01-19

申请人： Masumi Kubo ,  Akihiro Yamamoto ,  Takashi Ochi ,  Tetsuhiro Yamaguchi ,  Naoshi Yamada ,  Katsuhiko Morishita ,  Kiyoshi Ogishima ,  Kazuhiro Maekawa

发明人： Masumi Kubo ,  Akihiro Yamamoto ,  Takashi Ochi ,  Tetsuhiro Yamaguchi ,  Naoshi Yamada ,  Katsuhiko Morishita ,  Kiyoshi Ogishima ,  Kazuhiro Maekawa

IPC分类号： G02F1/133

CPC分类号： G02F1/133707 ,  G02F1/134336 ,  G02F1/136259 ,  G02F1/1393 ,  G02F2001/133742

摘要： The liquid crystal display device of this invention includes a plurality of picture element regions each defined by a first electrode provided on a face of a first substrate facing a liquid crystal layer and a second electrode provided on a second substrate so as to oppose the first electrode via the liquid crystal layer sandwiched therebetween. In each of the picture element regions, the first electrode has a plurality of openings and a solid portion, the liquid crystal layer is in a vertical orientation state when no voltage is applied between the first electrode and the second electrode, and when a voltage is applied between the first electrode and the second electrode, a plurality of liquid crystal domains each in a radially-inclined orientation state are respectively formed in the plurality of openings and the solid portion by inclined electrode fields generated at respective edge portions of the openings of the first electrode.

摘要翻译： 本发明的液晶显示装置包括多个像素区域，每个像素区域由设置在面向液晶层的第一基板的表面上的第一电极和设置在第二基板上的与第一电极相对的第二电极限定 通过夹在其间的液晶层。 在每个像素区域中，第一电极具有多个开口和实心部分，当在第一电极和第二电极之间没有施加电压时，液晶层处于垂直取向状态，并且当电压为 施加在第一电极和第二电极之间，在多个开口中分别形成各自处于径向倾斜取向状态的多个液晶畴，并且固体部分通过在第一电极和第二电极的开口的各个边缘部分处产生的倾斜电极场分别形成 第一电极。

公开(公告)号：US07613066B2

公开(公告)日：2009-11-03

申请号：US11477719

申请日：2006-06-30

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

IPC分类号： G11C8/00

CPC分类号： G09G3/3685 ,  G09G2300/0426 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2360/12

摘要： In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.

摘要翻译： 在集成电路装置中，数据线驱动器模块，其基于从RAM数据块提供的数据驱动显示面板的数据线，数据被读取N次（N为大于1的整数）N 显示面板包括沿位线延伸的第一方向设置的第一至第N分割数据线驱动器块。 当从RAM块提供的数据是M位（M是大于1的整数）并且与数据线相对应的像素的灰度级是G位时，第一至第N划分数据线驱动器块中的每一个包括（M / G）（三个的三个）数据线驱动器单元驱动（M / G）数据线。 （M / 3G）R数据线驱动器单元设置在第一细分驱动器中，（M / 3G）G数据线驱动器单元设置在第二细分驱动器中，并且（M / 3G）B数据线驱动器单元设置在 第三个细分驱动程序。

公开(公告)号：US07522441B2

公开(公告)日：2009-04-21

申请号：US11270553

申请日：2005-11-10

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

IPC分类号： G11C5/06

CPC分类号： G09G3/2096 ,  G09G3/3666 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2360/18

摘要： An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a high-speed interface circuit block HB which transfers data through a serial bus using differential signals, and a circuit block other than HB. The high-speed interface circuit block HB is disposed as an Mth circuit block CBM (2≦M≦N−1) of the circuit blocks CB1 to CBN.

摘要翻译： 一种集成电路装置，包括沿着第一方向D1设置的第一至第N电路块CB1至CBN，当第一方向D1是从集成电路器件的第一侧朝向与第一侧相反的第三侧的方向时， 第一侧为短边，当第二方向D2为从集成电路器件的第二侧向与第二侧相反的第四侧的方向时，第二侧为长边。 电路块CB1至CBN包括通过使用差分信号的串行总线传送数据的高速接口电路块HB以及HB以外的电路块。 高速接口电路块HB被布置为电路块CB1至CBN的第M个电路块CBM（2 <= M <= N-1）。

公开(公告)号：US07492659B2

公开(公告)日：2009-02-17

申请号：US11270586

申请日：2005-11-10

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa

IPC分类号： G11C5/14

CPC分类号： H01L23/552 ,  G11C5/063 ,  H01L24/49 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01037 ,  H01L2924/01066 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2224/45099

摘要： An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects for supplying a first power supply voltage to a plurality of memory cells are provided in a metal interconnect layer in which a plurality of bitlines are formed; wherein a second power supply interconnect for supplying a second power supply voltage to the memory cells is provided in a metal interconnect layer in which a plurality of wordlines are formed, the second power supply voltage being higher than the first power supply voltage; wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is provided in a layer above the bitline protection interconnects, the third power supply voltage being higher than the second power supply voltage.

摘要翻译： 一种具有显示存储器的集成电路器件，其中在形成多个位线的金属互连层中提供用于向多个存储单元提供第一电源电压的多个第一电源互连件; 其中在形成有多个字线的金属互连层中提供用于向所述存储单元提供第二电源电压的第二电源互连，所述第二电源电压高于所述第一电源电压; 其中多个位线保护互连形成在所述位线上方的层中，所述位线保护互连中的每一个在平面图中至少部分地覆盖所述位线之一; 并且其中，用于将第三电源电压提供给除了所述显示存储器之外的所述集成电路装置的电路的第三电源互连设置在所述位线保护互连线上方的层中，所述第三电源电压高于所述第二电源电压 。

公开(公告)号：US20070139594A1

公开(公告)日：2007-06-21

申请号：US11705515

申请日：2007-02-13

申请人： Masumi Kubo ,  Akihiro Yamamoto ,  Kiyoshi Ogishima ,  Takashi Ochi ,  Kazuhiro Maekawa

发明人： Masumi Kubo ,  Akihiro Yamamoto ,  Kiyoshi Ogishima ,  Takashi Ochi ,  Kazuhiro Maekawa

IPC分类号： G02F1/1337

CPC分类号： G02F1/133707 ,  G02F1/133555 ,  G02F1/1393 ,  G02F2201/128

摘要： The liquid crystal display device of the present invention includes a first substrate, a second substrate, and a vertical alignment type liquid crystal layer provided between the first substrate and the second substrate, and includes a plurality of picture element regions each defined by a first electrode provided on one side of the first substrate that is closer to the liquid crystal layer and a second electrode provided on the second substrate so as to oppose the first electrode via the liquid crystal layer. The first substrate includes a first orientation-regulating structure in each of the plurality of picture element regions, the first orientation-regulating structure exerting an orientation-regulating force so as to form a plurality of liquid crystal domains in the liquid crystal layer, each of the liquid crystal domains taking a radially-inclined orientation in the presence of an applied voltage. The second substrate includes a second orientation-regulating structure in a region corresponding to at least one of the plurality of liquid crystal domains, the second orientation-regulating structure exerting an orientation-regulating force for orienting liquid crystal molecules in at least one liquid crystal domain into a radially-inclined orientation at least in the presence of an applied voltage.

公开(公告)号：US20070013707A1

公开(公告)日：2007-01-18

申请号：US11477719

申请日：2006-06-30

申请人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

发明人： Satoru Kodaira ,  Noboru Itomi ,  Shuji Kawaguchi ,  Takashi Kumagai ,  Junichi Karasawa ,  Satoru Ito ,  Masahiko Moriguchi ,  Kazuhiro Maekawa

IPC分类号： G09G5/36

CPC分类号： G09G3/3685 ,  G09G2300/0426 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2360/12

摘要： In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.

摘要翻译： 在集成电路装置中，数据线驱动器模块，其基于从RAM数据块提供的数据驱动显示面板的数据线，数据被读取N次（N为大于1的整数）N 显示面板包括沿位线延伸的第一方向设置的第一至第N分割数据线驱动器块。 当从RAM块提供的数据是M位（M是大于1的整数）并且与数据线相对应的像素的灰度级是G位时，第一至第N划分数据线驱动器块中的每一个包括（M / G）（三个的三个）数据线驱动器单元驱动（M / G）数据线。 （M / 3G）R数据线驱动器单元设置在第一细分驱动器中，（M / 3G）G数据线驱动器单元设置在第二细分驱动器中，并且（M / 3G）B数据线驱动单元 第三个细分驱动程序。