公开(公告)号：US06448989B1

公开(公告)日：2002-09-10

申请号：US08935699

申请日：1997-09-23

申请人： Yasushi Shimizu ,  Masanobu Saito ,  Gaku Konishi ,  Hiroshi Sato

发明人： Yasushi Shimizu ,  Masanobu Saito ,  Gaku Konishi ,  Hiroshi Sato

IPC分类号： B41J2385

CPC分类号： G06K15/1209

摘要： The present invention relates to an image forming apparatus in which an electrostatic latent image is formed on an electrophotographic photosensitive member with digital light, and electrostatically developed with a developer to form a developed image. The apparatus has an exposure device for normally increasing the reflection density only in a specified region on the photosensitive member in a white image portion where no image is basically formed, in the horizontal scanning direction of the digital light. For example, a small amount of developer is supplied to either end of the photosensitive member having the tendency that the amount of the developer supplied is small, thereby preventing the occurrence of image flow at either end.

摘要翻译： 本发明涉及一种图像形成装置，其中静电潜像用数字光形成在电子照相感光构件上，并用显影剂静电显影以形成显影图像。 该装置具有仅在数字光的水平扫描方向上仅在基本形成图像的白色图像部分中的感光构件的特定区域中正常增加反射浓度的曝光装置。 例如，少量的显影剂被供给到感光构件的任一端，其倾向于提供的显影剂的量很小，从而防止在任一端发生图像流动。

公开(公告)号：US06272306B1

公开(公告)日：2001-08-07

申请号：US09416947

申请日：1999-10-13

申请人： Masanobu Saito ,  Keiji Okano ,  Gaku Konishi ,  Yasushi Shimizu ,  Hiroshi Satoh ,  Akira Domon ,  Satoru Motohashi

发明人： Masanobu Saito ,  Keiji Okano ,  Gaku Konishi ,  Yasushi Shimizu ,  Hiroshi Satoh ,  Akira Domon ,  Satoru Motohashi

IPC分类号： G03G1509

CPC分类号： G03G9/0819 ,  G03G9/097 ,  G03G13/09

摘要： A developing apparatus includes a developer bearing member for bearing and carrying developer to a developing area. A developer is borne on the developer bearing member, wherein the developer has a weight average particle size not exceeding 6.5 &mgr;m and contains an external additive of a charging polarity opposite to that of the developer. A voltage application device applies a voltage to the developer bearing member, wherein the voltage including at least a first voltage V1 for acting on the developer in a direction from the developer bearing member toward an image bearing member and a second voltage V2 for acting on the developer in a direction from an image bearing member toward said developer bearing member, and a charged potential VL of the image bearing member, a latent image potential VD a distance H between the developer bearing member and an image bearing member, and wherein the voltages V1 and V2 satisfy a following relationships: |V1−VL|/H≦3.7×10−6 V/m; and |V2−VD|/H≦2.9×10−6 V/m.

摘要翻译： 显影装置包括用于将显影剂承载并承载在显影区域上的显影剂承载部件。 显影剂承载在显影剂承载构件上，其中显影剂的重均粒径不超过6.5μm，并且包含与显影剂相反的充电极性的外部添加剂。 电压施加装置向显影剂承载部件施加电压，其中包括至少第一电压V1的电压在显影剂承载部件朝向图像承载部件的方向上作用在显影剂上，以及第二电压V2用于作用在显影剂承载部件上 显影剂从图像承载部件朝向显影剂承载部件的方向以及图像承载部件的带电电位VL，潜像电位VD，显影剂承载部件和图像承载部件之间的距离H，并且其中电压V1 V2满足以下关系：

公开(公告)号：US6167212A

公开(公告)日：2000-12-26

申请号：US401371

申请日：1999-09-22

申请人： Hiroshi Satoh ,  Keiji Okano ,  Masanobu Saito ,  Gaku Konishi ,  Yasushi Shimizu ,  Akira Domon ,  Satoru Motohashi

发明人： Hiroshi Satoh ,  Keiji Okano ,  Masanobu Saito ,  Gaku Konishi ,  Yasushi Shimizu ,  Akira Domon ,  Satoru Motohashi

IPC分类号： G03G15/06 ,  G03G15/08

CPC分类号： G03G15/065 ,  G03G2215/0614

摘要： The present invention relates to a development density adjusting method in which development density is adjusted by varying ratio of application time of a voltage having the first voltage value to application time of a voltage having the second voltage value in one period, and difference between a potential of the developer bearing member and a potential of the electrostatic latent image, when the voltage having the first voltage value is applied to the developer bearing member.

摘要翻译： 发明密度调整方法技术领域本发明涉及一种开发密度调整方法，其中，通过使具有第一电压值的电压的施加时间与具有一个周期中的第二电压值的电压的施加时间的变化比例， 当具有第一电压值的电压被施加到显影剂承载部件上时，显影剂承载部件的电位和静电潜像的电位。

公开(公告)号：US20050116459A1

公开(公告)日：2005-06-02

申请号：US10506546

申请日：2003-03-04

申请人： Jun Ito ,  Fumitaka Matsumoto ,  Masanobu Saito ,  Hiroshi Sato

发明人： Jun Ito ,  Fumitaka Matsumoto ,  Masanobu Saito ,  Hiroshi Sato

IPC分类号： B62D25/20 ,  B62D21/02 ,  B62D21/17 ,  B62D21/00

CPC分类号： B62D21/02

摘要： A leaf spring bracket is fixed to an outer surface of a vertical wall of a side member in a vehicle transverse direction by use of rivets penetrating the vertical wall. A gusset which couples an end of a cross member in the vehicle transverse direction with the side member has a vertical plate and upper and lower horizontal plates. The vertical plate is fixed to the vertical wall of the side member. The upper and lower horizontal plates extend inward in the vehicle transverse direction from upper and lower ends of the vertical plate, respectively, and are fixed to upper and lower walls of the cross member, respectively. The vertical plate has ribs protruding inward in the vehicle transverse direction. The ribs form and define recessed parts in an outer surface of the vertical plate in the vehicle transverse direction. Parts of the rivets, which project from an inner surface of the vertical wall in the vehicle transverse direction, are housed in the recessed parts. Thus, the vertical plate is fixed in a state of coming into surface contact with the inner surface of the vertical wall in the vehicle transverse direction.

摘要翻译： 板簧支架通过使用穿过垂直壁的铆钉在车辆横向上固定到侧构件的垂直壁的外表面。 将横向构件的车辆横向端部与侧部构件联接的角撑板具有竖直板和上部和下部水平板。 垂直板固定在侧构件的垂直壁上。 上下水平板分别从垂直板的上端和下端在车辆横向方向上向内延伸，分别固定在横梁的上壁和下壁上。 垂直板具有在车辆横向方向上向内突出的肋。 肋在车辆横向上形成并限定在垂直板的外表面中的凹陷部分。 从车宽方向的垂直壁的内表面突出的铆钉的部分容纳在凹部中。 因此，垂直板在与车辆横向的垂直壁的内表面接触的状态下被固定。

公开(公告)号：US07261322B2

公开(公告)日：2007-08-28

申请号：US10506546

申请日：2003-03-04

申请人： Jun Ito ,  Fumitaka Matsumoto ,  Masanobu Saito ,  Hiroshi Sato

发明人： Jun Ito ,  Fumitaka Matsumoto ,  Masanobu Saito ,  Hiroshi Sato

IPC分类号： B62D21/02 ,  B62D21/11

CPC分类号： B62D21/02

摘要： A leaf spring bracket is fixed to an outer surface of a vertical wall of a side member in a vehicle transverse direction by use of rivets penetrating the vertical wall. A gusset which couples an end of a cross member in the vehicle transverse direction with the side member has a vertical plate and upper and lower horizontal plates. The vertical plate is fixed to the vertical wall of the side member. The upper and lower horizontal plates extend inward in the vehicle transverse direction from upper and lower ends of the vertical plate, respectively, and are fixed to upper and lower walls of the cross member, respectively. The vertical plate has ribs protruding inward in the vehicle transverse direction. The ribs form and define recessed parts in an outer surface of the vertical plate in the vehicle transverse direction. Parts of the rivets, which project from an inner surface of the vertical wall in the vehicle transverse direction, are housed in the recessed parts. Thus, the vertical plate is fixed in a state of coming into surface contact with the inner surface of the vertical wall in the vehicle transverse direction.

摘要翻译： 板簧支架通过使用穿过垂直壁的铆钉在车辆横向上固定到侧构件的垂直壁的外表面。 将横向构件的车辆横向端部与侧部构件联接的角撑板具有竖直板和上部和下部水平板。 垂直板固定在侧构件的垂直壁上。 上下水平板分别从垂直板的上端和下端在车辆横向方向上向内延伸，并分别固定在横梁的上壁和下壁上。 垂直板具有在车辆横向方向上向内突出的肋。 肋在车辆横向上形成并限定在垂直板的外表面中的凹陷部分。 从车宽方向的垂直壁的内表面突出的铆钉的部分容纳在凹部中。 因此，垂直板在与车辆横向的垂直壁的内表面接触的状态下被固定。

公开(公告)号：US20080119021A1

公开(公告)日：2008-05-22

申请号：US12007751

申请日：2008-01-15

申请人： Yoshio Ozawa ,  Shigehiko Saida ,  Yuji Takeuchi ,  Masanobu Saito

发明人： Yoshio Ozawa ,  Shigehiko Saida ,  Yuji Takeuchi ,  Masanobu Saito

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

摘要翻译： 半导体器件包括半导体衬底和设置在半导体衬底上的非易失性存储单元，所述非易失性存储单元包括隧道绝缘膜，所述隧道绝缘膜具有在非易失性的沟道宽度方向周期性且连续变化的膜厚度 存储单元，设置在隧道绝缘膜上的浮置栅电极，设置在浮置栅电极上方的控制栅电极，以及设置在控制栅电极和浮栅之间的电极间绝缘膜。

公开(公告)号：US20080048250A1

公开(公告)日：2008-02-28

申请号：US11846369

申请日：2007-08-28

申请人： Hisayo MOMOSE ,  Hiroshi Iwai ,  Masanobu Saito ,  Tatsuya Ohguro ,  Mizuki Ono ,  Takashi Yoshitomi ,  Shinichi Nakamura

发明人： Hisayo MOMOSE ,  Hiroshi Iwai ,  Masanobu Saito ,  Tatsuya Ohguro ,  Mizuki Ono ,  Takashi Yoshitomi ,  Shinichi Nakamura

IPC分类号： H01L27/06

CPC分类号： H01L29/66575 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/28211 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/78

摘要： A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 μm; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.

摘要翻译： 半导体器件包括：p型半导体衬底（1）; 绝缘膜（3）; 经由所述绝缘膜形成在所述基板上的栅电极（2） 以及形成在形成在基板（1）上的栅电极（2）下方的沟道形成区域（4）的两侧的n型源极/漏极区域（5）。 特别地，在氧化硅膜的转换率（氧化硅当量厚度）下，确定绝缘膜（3）的厚度（T×OX ）小于2.5nm。 栅极（2）的栅极长度（L SUB）确定为等于或小于0.3μm; 并且进一步施加到栅极（2）和漏极区（6）的电压被确定为1.5V或更小。 因此，在具有隧穿栅极氧化膜（3）的MOSFET中，可以提高热载流子应力下的晶体管的可靠性，并且可以显着降低栅极漏电流，从而可以显着提高晶体管特性。

公开(公告)号：US06929990B2

公开(公告)日：2005-08-16

申请号：US10681318

申请日：2003-10-09

申请人： Hisayo Momose ,  Hiroshi Iwai ,  Masanobu Saito ,  Tatsuya Ohguro ,  Mizuki Ono ,  Takashi Yoshitomi ,  Shinichi Nakamura

发明人： Hisayo Momose ,  Hiroshi Iwai ,  Masanobu Saito ,  Tatsuya Ohguro ,  Mizuki Ono ,  Takashi Yoshitomi ,  Shinichi Nakamura

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L27/088 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/28211 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/78

摘要： A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 μm; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.

摘要翻译： 半导体器件包括：p型半导体衬底（1）; 绝缘膜（3）; 经由所述绝缘膜形成在所述基板上的栅电极（2） 以及形成在形成在基板（1）上的栅电极（2）下方的沟道形成区域（4）的两侧的n型源极/漏极区域（5）。 特别地，在氧化硅膜的转换率（氧化硅当量厚度）下，确定绝缘膜（3）的厚度（T×OX ）小于2.5nm。 栅极（2）的栅极长度（L SUB）确定为等于或小于0.3μm; 并且进一步施加到栅极（2）和漏极区（6）的电压被确定为1.5V或更小。 因此，在具有隧穿栅极氧化膜（3）的MOSFET中，可以提高热载流子应力下的晶体管的可靠性，并且可以显着降低栅极漏电流，从而可以显着提高晶体管特性。

公开(公告)号：US06410952B1

公开(公告)日：2002-06-25

申请号：US09828205

申请日：2001-04-09

申请人： Hisayo Momose ,  Hiroshi Iwai ,  Masanobu Saito ,  Tatsuya Ohguro ,  Mizuki Ono ,  Takashi Yoshitomi ,  Shinichi Nakamura

发明人： Hisayo Momose ,  Hiroshi Iwai ,  Masanobu Saito ,  Tatsuya Ohguro ,  Mizuki Ono ,  Takashi Yoshitomi ,  Shinichi Nakamura

IPC分类号： H01L2976

摘要： A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.

公开(公告)号：US5903027A

公开(公告)日：1999-05-11

申请号：US910222

申请日：1997-08-13

申请人： Takashi Yoshitomi ,  Masanobu Saito ,  Hisayo Momose ,  Hiroshi Iwai ,  Yukihiro Ushiku ,  Mizuki Ono ,  Yasushi Akasaka ,  Hideaki Nii ,  Satoshi Matsuda ,  Yasuhiro Katsumata ,  Tatsuya Ooguro ,  Claudio Fiegna

发明人： Takashi Yoshitomi ,  Masanobu Saito ,  Hisayo Momose ,  Hiroshi Iwai ,  Yukihiro Ushiku ,  Mizuki Ono ,  Yasushi Akasaka ,  Hideaki Nii ,  Satoshi Matsuda ,  Yasuhiro Katsumata ,  Tatsuya Ooguro ,  Claudio Fiegna

IPC分类号： H01L21/033 ,  H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/0338 ,  H01L21/2255 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/823814 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66628

摘要： A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j �nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff �nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.

摘要翻译： MOS型半导体器件具有长度为170nm（0.17μm）以下的栅极，沟道附近的源极和漏极扩散层的结深度为22nm以下，表面上的杂质浓度 在源极和漏极扩散层中形成1020cm-3以上。 这种结构使用从950℃到1050℃的热范围的固相扩散和/或通过灰化或蚀刻使栅极宽度变窄来获得。 其他MOS型半导体器件的特征在于源极和漏极扩散层区域中的结深度xj [nm]与有效沟道长度Leff [nm]之间的关系由Leff> 0.69×j-6.17确定。