公开(公告)号：US20090032965A1

公开(公告)日：2009-02-05

申请号：US12216808

申请日：2008-07-10

申请人： Yasushi Urakami ,  Hitoshi Yamaguchi ,  Jun Sakakibara

发明人： Yasushi Urakami ,  Hitoshi Yamaguchi ,  Jun Sakakibara

IPC分类号： H01L23/48

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a first semiconductor layer; a p-n column portion over the first semiconductor layer and including second and third semiconductor layers, which are alternately arranged; and a peripheral portion adjacently to the p-n column portion and including a fourth semiconductor layer. An end second semiconductor layer has an impurity amount equal to or larger than a half of other second semiconductor layers. The third semiconductor layers include a large impurity amount portion adjacent to the end second semiconductor layer. The large impurity amount portion includes at least one third semiconductor layer having an impurity amount larger than an impurity amount of other third semiconductor layers.

摘要翻译： 一种半导体器件包括：第一半导体层; 在第一半导体层上的p-n列部分，并且包括交替布置的第二和第三半导体层; 以及与p-n列部分相邻并包括第四半导体层的周边部分。 端部第二半导体层的杂质量等于或大于其它第二半导体层的一半。 第三半导体层包括与端部第二半导体层相邻的大杂质量部分。 大杂质量部分包括杂质量大于其它第三半导体层的杂质量的至少一个第三半导体层。

公开(公告)号：US07838995B2

公开(公告)日：2010-11-23

申请号：US12216808

申请日：2008-07-10

申请人： Yasushi Urakami ,  Hitoshi Yamaguchi ,  Jun Sakakibara

发明人： Yasushi Urakami ,  Hitoshi Yamaguchi ,  Jun Sakakibara

IPC分类号： H01L23/48

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a first semiconductor layer; a p-n column portion over the first semiconductor layer and including second and third semiconductor layers, which are alternately arranged; and a peripheral portion adjacently to the p-n column portion and including a fourth semiconductor layer. An end second semiconductor layer has an impurity amount equal to or larger than a half of other second semiconductor layers. The third semiconductor layers include a large impurity amount portion adjacent to the end second semiconductor layer. The large impurity amount portion includes at least one third semiconductor layer having an impurity amount larger than an impurity amount of other third semiconductor layers.

摘要翻译： 一种半导体器件包括：第一半导体层; 在第一半导体层上的p-n列部分，并且包括交替布置的第二和第三半导体层; 以及与p-n列部分相邻并包括第四半导体层的周边部分。 端部第二半导体层的杂质量等于或大于其它第二半导体层的一半。 第三半导体层包括与端部第二半导体层相邻的大杂质量部分。 大杂质量部分包括杂质量大于其它第三半导体层的杂质量的至少一个第三半导体层。

公开(公告)号：US07564095B2

公开(公告)日：2009-07-21

申请号：US11439971

申请日：2006-05-25

申请人： Yasushi Urakami ,  Jun Sakakibara ,  Hitoshi Yamaguchi

发明人： Yasushi Urakami ,  Jun Sakakibara ,  Hitoshi Yamaguchi

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/66704 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7823 ,  H01L29/7825

摘要： A semiconductor device includes: a semiconductor substrate; an element region having a semiconductor element including an impurity layer and a trench, wherein the impurity layer is disposed in the trench, and wherein the trench is disposed on a main surface of the substrate; and a field region disposed around the element region. The trench is an aggregation of a plurality of stripe line trenches so that the element region has a polygonal shape. The field region includes a dummy trench disposed along with one side of the polygonal shape on a periphery of the element region. The dummy trench has a width and a longitudinal direction, which are equal to those of the trench. The field region further includes an impurity layer disposed in the dummy trench.

摘要翻译： 半导体器件包括：半导体衬底; 具有包括杂质层和沟槽的半导体元件的元件区，其中所述杂质层设置在所述沟槽中，并且其中所述沟槽设置在所述衬底的主表面上; 以及设置在所述元件区域周围的场区域。 沟槽是多个条纹沟槽的聚集，使得元件区域具有多边形形状。 场区域包括在元件区域的周边上与多边形形状的一侧一起设置的虚拟沟槽。 虚拟沟槽具有与沟槽相同的宽度和纵向方向。 场区域还包括设置在虚拟沟槽中的杂质层。

公开(公告)号：US20060286751A1

公开(公告)日：2006-12-21

申请号：US11439971

申请日：2006-05-25

申请人： Yasushi Urakami ,  Jun Sakakibara ,  Hitoshi Yamaguchi

发明人： Yasushi Urakami ,  Jun Sakakibara ,  Hitoshi Yamaguchi

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/66704 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7823 ,  H01L29/7825

摘要： A semiconductor device includes: a semiconductor substrate; an element region having a semiconductor element including an impurity layer and a trench, wherein the impurity layer is disposed in the trench, and wherein the trench is disposed on a main surface of the substrate; and a field region disposed around the element region. The trench is an aggregation of a plurality of stripe line trenches so that the element region has a polygonal shape. The field region includes a dummy trench disposed along with one side of the polygonal shape on a periphery of the element region. The dummy trench has a width and a longitudinal direction, which are equal to those of the trench. The field region further includes an impurity layer disposed in the dummy trench.

公开(公告)号：US07063751B2

公开(公告)日：2006-06-20

申请号：US10132298

申请日：2002-04-26

申请人： Yasushi Urakami ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Nobuhiro Tsuji

发明人： Yasushi Urakami ,  Shoichi Yamauchi ,  Hitoshi Yamaguchi ,  Nobuhiro Tsuji

IPC分类号： H01L29/12 ,  H01L29/30 ,  H01L21/20 ,  H01L21/36 ,  H01L29/04

CPC分类号： H01L21/763 ,  H01L21/30608 ,  H01L21/761

摘要： A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that the width of the mask opening width is greater than the width of the trench. After that, the inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished to complete the substrate.

摘要翻译： 通过由形成在半导体衬底上的氧化硅膜构成的掩模，在半导体衬底中形成沟槽。 然后，蚀刻掩模的开口部分的边缘部分，使得掩模开口宽度的宽度大于沟槽的宽度。 之后，通过在低压下在非氧化或非氮化气氛中在1000℃左右的热处理使沟槽的内表面平滑化。 然后，沟槽填充有外延膜。 之后，抛光外延膜以完成基板。

公开(公告)号：US06406982B2

公开(公告)日：2002-06-18

申请号：US09870705

申请日：2001-06-01

申请人： Yasushi Urakami ,  Shoichi Yamauchi ,  Toshio Sakakibara ,  Hitoshi Yamaguchi ,  Nobuhiro Tsuji

发明人： Yasushi Urakami ,  Shoichi Yamauchi ,  Toshio Sakakibara ,  Hitoshi Yamaguchi ,  Nobuhiro Tsuji

IPC分类号： H01L2120

CPC分类号： H01L21/763 ,  H01L21/30608 ,  H01L21/761

摘要： A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that an opening width thereof is wider than that of the trench. After that, an inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished, whereby a semiconductor substrate for forming a semiconductor device is obtained.

摘要翻译： 通过由形成在半导体衬底上的氧化硅膜构成的掩模，在半导体衬底中形成沟槽。 然后，蚀刻掩模的开口部分的边缘部分，使得其开口宽度比沟槽的宽度宽。 之后，通过在低压下在非氧化或非氮化气氛中在1000℃左右的热处理使沟槽的内表面平滑化。 然后，沟槽填充有外延膜。 之后，对该外延膜进行研磨，得到半导体装置的半导体基板。

公开(公告)号：US09051663B2

公开(公告)日：2015-06-09

申请号：US13305019

申请日：2011-11-28

申请人： Yasushi Urakami ,  Ayumu Adachi ,  Itaru Gunjishima

发明人： Yasushi Urakami ,  Ayumu Adachi ,  Itaru Gunjishima

IPC分类号： C30B23/00 ,  C30B29/36 ,  C30B23/02 ,  H01L29/16

CPC分类号： C30B29/36 ,  C30B23/00 ,  C30B23/025 ,  H01L29/1608

摘要： A manufacturing method of a SiC single crystal includes a first growth process and a re-growth process. In the first growth process, a first seed crystal made of SiC is used to grow a first SiC single crystal. In the re-growth process, a plurality of growth steps is performed for (n−1) times. In a k-th growth step, a k-th seed crystal is cut out from a grown (k−1)-th SiC single crystal, and the k-th seed crystal is used to grow a k-th SiC single crystal (n≧2 and 2≦k≦n). When an offset angle of a growth surface of the k-th seed crystal is defined as θk, at least in one of the plurality of growth steps, the offset angle θk is smaller than the offset angle θk-1.

摘要翻译： SiC单晶的制造方法包括第一生长工序和再生长工序。 在第一生长过程中，使用由SiC制成的第一晶种来生长第一SiC单晶。 在再生长过程中，进行多次生长步骤（n-1次）。 在第k个生长步骤中，从生长的（k-1）SiC单晶中切出第k个晶种，并且将第k个晶种用于生长第k个SiC单晶（ n≥2和2＆nlE; k＆nlE; n）。 当第k种子晶体的生长表面的偏移角被定义为＆amp; k时，至少在多个生长步骤中的一个中，偏移角度θ小于偏移角度θ-k 。

公开(公告)号：US20140091325A1

公开(公告)日：2014-04-03

申请号：US14119710

申请日：2012-06-04

申请人： Itaru Gunjishima ,  Keisuke Shigetoh ,  Yasushi Urakami ,  Masanori Yamada ,  Ayumu Adachi ,  Masakazu Kobayashi

发明人： Itaru Gunjishima ,  Keisuke Shigetoh ,  Yasushi Urakami ,  Masanori Yamada ,  Ayumu Adachi ,  Masakazu Kobayashi

IPC分类号： C30B23/02 ,  C30B29/36 ,  H01L29/16

CPC分类号： C30B23/025 ,  C30B23/005 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02587 ,  H01L21/02609 ,  H01L29/1608 ,  Y10T428/21

摘要： When an SiC single crystal having a large diameter of a {0001} plane is produced by repeating a-plane growth, the a-plane growth of the SiC single crystal is carried out so that a ratio Sfacet (=S1×100/S2) of an area (S1) of a Si-plane side facet region to a total area (S2) of the growth plane is maintained at 20% or less.

摘要翻译： 当通过重复a面生长产生具有{0001}面大直径的SiC单晶时，进行SiC单晶的a面生长，使得Sfacet（= S1×100 / S2） 的Si平面侧面面积（S1）与生长面的总面积（S2）保持在20％以下。

公开(公告)号：US20120132132A1

公开(公告)日：2012-05-31

申请号：US13305019

申请日：2011-11-28

申请人： Yasushi Urakami ,  Ayumu Adachi ,  Itaru Gunjishima

发明人： Yasushi Urakami ,  Ayumu Adachi ,  Itaru Gunjishima

IPC分类号： C30B23/02

CPC分类号： C30B29/36 ,  C30B23/00 ,  C30B23/025 ,  H01L29/1608

摘要： A manufacturing method of a SiC single crystal includes a first growth process and a re-growth process. In the first growth process, a first seed crystal made of SiC is used to grow a first SiC single crystal. In the re-growth process, a plurality of growth steps is performed for (n−1) times. In a k-th growth step, a k-th seed crystal is cut out from a grown (k−1)-th SiC single crystal, and the k-th seed crystal is used to grow a k-th SiC single crystal (n≧2 and 2≦k≦n). When an offset angle of a growth surface of the k-th seed crystal is defined as θk, at least in one of the plurality of growth steps, the offset angle θk is smaller than the offset angle θk−1.

摘要翻译： SiC单晶的制造方法包括第一生长工序和再生长工序。 在第一生长过程中，使用由SiC制成的第一晶种来生长第一SiC单晶。 在再生长过程中，进行多次生长步骤（n-1次）。 在第k个生长步骤中，从生长的（k-1）SiC单晶中切出第k个晶种，并且将第k个晶种用于生长第k个SiC单晶（ n≥2和2＆nlE; k＆nlE; n）。 当第k种子晶体的生长表面的偏移角被定义为＆amp; k时，至少在多个生长步骤中的一个中，偏移角度θ小于偏移角度θ-k 。

公开(公告)号：US20140027787A1

公开(公告)日：2014-01-30

申请号：US14110574

申请日：2012-05-16

申请人： Itaru Gunjishima ,  Yasushi Urakami ,  Ayumu Adachi

发明人： Itaru Gunjishima ,  Yasushi Urakami ,  Ayumu Adachi

IPC分类号： H01L29/30 ,  H01L29/16

CPC分类号： H01L29/30 ,  C30B23/025 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/861

摘要： An SiC single crystal having at least one orientation region where a basal plane dislocation has a high linearity and is oriented to three crystallographically-equivalent directions, and an SiC wafer and a semiconductor device which are manufactured from the SiC single crystal. The SiC single crystal can be manufactured by using a seed crystal in which the offset angle on a {0001} plane uppermost part side is small and the offset angle on an offset direction downstream side is large and growing another crystal on the seed crystal.

摘要翻译： 具有至少一个取向区域的​​SiC单晶，其中基面位错具有高线性度并且取向为三个晶体上等同的<11-20>方向，以及由SiC单晶制造的SiC晶片和半导体器件 。 SiC单晶可以通过使用其中{0001}平面最上部分侧的偏移角小并且偏移方向下游侧的偏移角大并且在晶种上生长另一晶体的晶种来制造。