公开(公告)号：US5545580A

公开(公告)日：1996-08-13

申请号：US530746

申请日：1995-09-19

申请人： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

发明人： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

IPC分类号： H01L27/112 ,  H01L21/8246

CPC分类号： H01L27/112

摘要： A multi-state read-only-memory device and a method for fabricating the same is suitable for forming on a semiconductor substrate. The read-only memory device is provided with bit lines and word lines which are mutually intersecting. In accordance with the present invention, multiple polysilicon selective deposition procedures are utilized to form a plurality of protrusion portions onto the word lines but with multiple thicknesses. Then, one implantation procedure is applied to program the device into multiple states at the same time without incurring misalignment problems that result in inaccuracy.

摘要翻译： 多状态只读存储器件及其制造方法适用于在半导体衬底上形成。 只读存储器件具有相互相交的位线和字线。 根据本发明，利用多个多晶硅选择性沉积程序在字线上形成多个突出部分，但具有多个厚度。 然后，应用一个植入程序同时将器件编程成多个状态，而不会导致导致不准确的错位问题。

公开(公告)号：US5504030A

公开(公告)日：1996-04-02

申请号：US505050

申请日：1995-07-21

申请人： Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

发明人： Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

IPC分类号： H01L21/8246

CPC分类号： H01L27/11246 ,  Y10S438/981

摘要： A method of fabricating memory cells of a mask ROM device. A plurality of source/drain regions extending along a first direction is formed by implanting impurities into a semiconductor substrate, constituting bit lines of the memory cells. A code oxide layer is formed on a designated area of the semiconductor substrate defined by a barrier layer using a liquid-phase deposition process, whereby a multi-state mask ROM is fabricated by repeatedly performing the liquid-phase deposition process to form a series of coding oxide layers having increasing thicknesses. A gate oxide layer is formed on a portion of the semiconductor substrate not covered by the coding oxide layers. The thickness of the gate oxide layer is smaller than that of the coding oxide layers. A plurality of gate electrodes extending along a second direction orthogonal to the first direction is formed by depositing and patterning a conducting layer on the coding oxide layer and the gate oxide layer, constituting word lines of said memory cells. The cross area of every two adjacent bit lines and one word line thereby forms a memory cell of the mask ROM wherein threshold voltages of the memory cells are altered proportional to the thicknesses of the gate oxide layer and the coding oxide layers.

摘要翻译： 一种制造掩模ROM器件的存储单元的方法。 沿着第一方向延伸的多个源极/漏极区域通过将杂质注入构成存储器单元的位线的半导体衬底中而形成。 在通过液相沉积工艺由阻挡层限定的半导体衬底的指定区域上形成编码氧化物层，由此通过反复进行液相沉积工艺以形成一系列 编码具有增加的厚度的氧化物层。 在不被编码氧化物层覆盖的半导体衬底的一部分上形成栅氧化层。 栅极氧化物层的厚度小于编码氧化物层的厚度。 通过在构成所述存储单元的字线的编码氧化物层和栅极氧化物层上沉积和图案化导电层来形成沿着与第一方向正交的第二方向延伸的多个栅电极。 因此，每两个相邻位线和一个字线的横截面形成掩模ROM的存储单元，其中存储单元的阈值电压与栅极氧化物层和编码氧化物层的厚度成比例地变化。

公开(公告)号：US5756376A

公开(公告)日：1998-05-26

申请号：US652895

申请日：1996-05-23

申请人： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

发明人： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

IPC分类号： H01L21/768 ,  H01L23/485 ,  H05K1/00 ,  H05K1/03

CPC分类号： H01L24/05 ,  H01L21/768 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L24/45 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14

摘要： A method for removing a diffusion barrier layer on pad regions and diminishing the effect of plasma ions induced when removing a photoresist layer by a plasma asher. A two stage rapid thermal processing step is applied to the partially-removed diffusion barrier layer before a metal layer is formed. The first stage lasts a longer period of time at a lower temperature, for example, in the range of between 50 and 60 seconds at a temperature of about 600.degree. C. The second stage lasts a shorter period of time at a higher temperature, for example, in the range of between 20 and 30 seconds at a temperature of about 750.degree. C.

摘要翻译： 一种用于去除焊盘区域上的扩散阻挡层的方法，并且减少了通过等离子体灰化器去除光致抗蚀剂层时引起的等离子体离子的影响。 在形成金属层之前，将二阶段快速热处理步骤应用于部分去除的扩散阻挡层。 第一阶段在较低温度下持续更长的时间，例如在约600℃的温度下在50至60秒的范围内。第二阶段在较高温度下持续更短的时间段，对于 例如，在约750℃的温度下在20至30秒的范围内。

公开(公告)号：US5585297A

公开(公告)日：1996-12-17

申请号：US450298

申请日：1995-05-25

申请人： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

发明人： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

IPC分类号： H01L27/112 ,  H01L21/8246

CPC分类号： H01L27/112

摘要： This is a method of manufacturing a multiple state MASK ROM semiconductor device on a P-type semiconductor substrate. The substrate includes an array of parallel buried bit lines oriented in a first direction. The process includes forming a gate oxide layer over the substrate including the buried bit lines; word lines over the gate oxide layer oriented orthogonally to the direction of the array of bit lines. Then form a first patterned implant mask over the device with a first set of openings through the mask. Ion implant dopant of a first dosage level through the openings in the mask to form implant doped regions of a first dosage level in the substrate. Form a second patterned implant mask over the device with a second set of openings through the mask. Then ion implant a dopant of a second dosage level through the openings in the mask to form implanted doped regions of a second dosage level in the substrate, the second dosage level being substantially different from the first dosage level.

摘要翻译： 这是在P型半导体衬底上制造多状态MASK ROM半导体器件的方法。 衬底包括沿第一方向定向的平行掩埋位线阵列。 该方法包括在包括掩埋位线的衬底上形成栅氧化层; 栅极氧化物层上的字线与位线阵列的方向正交定向。 然后在装置上形成第一图案化植入物掩模，其中第一组开口穿过掩模。 通过掩模中的开口具有第一剂量水平的离子注入掺杂剂，以在衬底中形成第一剂量水平的注入掺杂区域。 在设备上形成第二图案化植入物掩模，其中第二组开口穿过掩模。 然后通过掩模中的开口离子注入第二剂量水平的掺杂剂，以在底物中形成第二剂量水平的注入的掺杂区域，第二剂量水平基本上不同于第一剂量水平。

公开(公告)号：US5859460A

公开(公告)日：1999-01-12

申请号：US839497

申请日：1997-04-14

申请人： Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

发明人： Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

IPC分类号： G11C11/56 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/1126 ,  G11C11/56 ,  G11C11/5692 ,  H01L27/112

摘要： A tri-state read-only memory device and its fabrication method are disclosed herein. After a plurality of word lines are formed and spaced apart in parallel through patterning by a shielding layer, insulating blocks are formed to fill the trenches among the word lines. Then removing the shielding layer, sidewalls, of the insulating blocks are revealed, and spacers are formed on the sidewalls thereof. The spacers above the first state regions are removed to form the conductive width of the channel regions in three forms. By merely applying one code-implantation, the ROM device are coded into on of three states at the same time. In addition, the disposition of the insulating blocks by liquid-phase deposition prevents the misalignment that often occurs with the conventional method.

摘要翻译： 本文公开了三态只读存储器件及其制造方法。 在通过屏蔽层构图形成多个字线并平行间隔开之后，形成绝缘块以填充字线之间的沟槽。 然后，去除绝缘块的屏蔽层侧壁，并且在其侧壁上形成间隔物。 去除第一状态区之上的间隔物以形成三种形式的沟道区的导电宽度。 通过仅仅应用一个代码注入，ROM设备被同时编码成三种状态。 此外，通过液相沉积的绝缘块的布置防止了常规方法经常发生的不对准。

公开(公告)号：US5693551A

公开(公告)日：1997-12-02

申请号：US530575

申请日：1995-09-19

申请人： Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

发明人： Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

IPC分类号： G11C11/56 ,  H01L21/8246 ,  H01L27/112

CPC分类号： H01L27/1126 ,  G11C11/56 ,  G11C11/5692 ,  H01L27/112

摘要： A tri-state read-only memory device and its fabrication method are disclosed herein. After a plurality of word lines are formed and spaced apart in parallel through patterning by a shielding layer, insulating blocks are formed to fill the trenches among the word lines. Then removing the shielding layer, sidewalls of the insulating blocks are revealed, and spacers are formed on the sidewalls thereof. The spacers above the first state regions are removed to form the conductive width of the channel regions in three forms. By merely applying one code-implantation, the ROM device are coded into on of three states at the same time. In addition, the disposition of the insulating blocks by liquid-phase deposition prevents the misalignment that often occurs with the conventional method.

摘要翻译： 本文公开了三态只读存储器件及其制造方法。 在通过屏蔽层构图形成多个字线并平行间隔开之后，形成绝缘块以填充字线之间的沟槽。 然后去除屏蔽层，揭示绝缘块的侧壁，并在其侧壁上形成间隔物。 去除第一状态区之上的间隔物以形成三种形式的沟道区的导电宽度。 通过仅仅应用一个代码注入，ROM设备被同时编码成三种状态。 此外，通过液相沉积的绝缘块的布置防止了常规方法经常发生的不对准。

公开(公告)号：US5668030A

公开(公告)日：1997-09-16

申请号：US524549

申请日：1995-09-07

申请人： Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

发明人： Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

IPC分类号： H01L21/8246 ,  H01L23/544

CPC分类号： H01L27/1126 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A process for fabricating identification alphanumeric code markings on the substrate of mask ROM devices is disclosed. The fabrication process comprises first forming a deposited layer on the substrate of the mask ROM device. A photoresist layer is then formed on the deposited layer. A photomask layer by is then shaped by forming a pattern on the photoresist layer that reveals the channel regions of the memory cell transistors to be programmed into the blocking state, as well as reveals the graphical pattern of the alphanumeric code marking. An etching procedure then removes the portion of the deposited layer revealing the graphical pattern of the alphanumeric code markings. The photomask layer is then removed. A code implantation procedure may precede or follow the etching procedure to facilitate the programming of the memory cells of the mask ROM device.

摘要翻译： 公开了一种用于在掩模ROM器件的衬底上制造识别字母数字代码标记的过程。 制造工艺包括首先在掩模ROM器件的衬底上形成沉积层。 然后在沉积层上形成光致抗蚀剂层。 然后通过在光致抗蚀剂层上形成图案来形成光掩模层，该图案将存储单元晶体管的通道区域显示为被编程成阻塞状态，以及揭示字母数字代码标记的图形图案。 然后，蚀刻过程去除沉积层的部分，露出字母数字代码标记的图形图案。 然后去除光掩模层。 代码注入过程可以在蚀刻过程之前或之后，以便于掩模ROM器件的存储器单元的编程。

公开(公告)号：US5597753A

公开(公告)日：1997-01-28

申请号：US364318

申请日：1994-12-27

申请人： Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

发明人： Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

IPC分类号： H01L21/8246

CPC分类号： H01L27/11246 ,  Y10S438/981

摘要： An improved Read-Only-Memory (ROM) structure and a method of manufacturing said ROM device structure having an ultra-high-density of coded ROM cells, was achieved. The array of programmed ROM cells are composed of a single field effect transistor (FET) in each ROM cell. The improved ROM process utilizes the patterning of a ROM code insulating layer over each coded FET (cell) that is selected to remain in an off-state (nonconducting) when a gate voltage is applied. The remaining FETs (cells) have a thin gate oxide which switch to the on-state (conducting) when a gate voltage is applied. The thick ROM code insulating layer eliminates the need to code the FETs in the ROM memory cells by conventional high dose ion implantation. This eliminated the counter-doping of the buried bit lines by the implantation allowing for much tighter ground rules for the spacing between buried bit line. The elimination of the implant also reduces substantially the stand-by leakage current that is so important in battery operated electronic equipment, such as lap-top computers. The gate capacitance of the off-state cells is also substantially reduced because of the thick insulating layer, thereby reducing the RC time delay in the word lines and improving circuit performance.

摘要翻译： 实现了改进的只读存储器（ROM）结构和制造具有超高密度编码ROM单元的所述ROM器件结构的方法。 编程ROM单元的阵列由每个ROM单元中的单个场效应晶体管（FET）构成。 改进的ROM处理利用在施加栅极电压时选择为保持在截止状态（非导通）的每个编码的FET（单元）上的ROM代码绝缘层的图案化。 当施加栅极电压时，剩余的FET（单元）具有薄的栅极氧化物，其切换到导通状态（导通）。 粗ROM代码绝缘层消除了通过常规高剂量离子注入对ROM存储单元中的FET进行编码的需要。 这通过注入消除了掩埋位线的反掺杂，允许掩埋位线之间的间隔更紧密的基本规则。 植入物的消除也大大降低了备用泄漏电流，这在电池供电的电子设备如笔记本电脑中如此重要。 由于厚的绝缘层，断态单元的栅极电容也显着减小，从而减小了字线中的RC时间延迟并提高了电路性能。

公开(公告)号：US5536669A

公开(公告)日：1996-07-16

申请号：US507698

申请日：1995-07-26

申请人： Kuan-Cheng Su ,  Yi-Chung Sheng ,  Chen-Hui Chung

发明人： Kuan-Cheng Su ,  Yi-Chung Sheng ,  Chen-Hui Chung

IPC分类号： H01L21/8246

CPC分类号： H01L27/11253

摘要： A method for fabricating ROM devices with self-aligned code implants comprises the steps of: forming an oxide layer over a silicon substrate; forming a plurality of deposition selecting strips over the oxide layer; forming a dielectric between the plurality of deposition selecting strips to thereby produce a plurality of dielectric strips; removing the deposition selecting strips; forming a number of code diffusion regions in the silicon substrate; and forming a plurality of word lines between the plurality of dielectric strips. Since the code diffusion regions are formed by implanting ions through the dielectric strips, the shielding of the dielectric strips can prevent the outspreading of impurities due to code mask mis-alignment. Therefore, the positions of code diffusion regions can be well controlled beneath the word lines.

摘要翻译： 用于制造具有自对准代码注入的ROM器件的方法包括以下步骤：在硅衬底上形成氧化物层; 在所述氧化物层上形成多个沉积选择条; 在所述多个沉积选择条之间形成电介质，从而产生多个介质条; 去除沉积选择条; 在硅衬底中形成多个代码扩散区域; 以及在所述多个介质条之间形成多个字线。 由于通过将介质条注入离子形成代码扩散区，所以介质条的屏蔽可以防止由于码屏错误对准而导致的杂质扩展。 因此，代码扩散区域的位置可以很好地控制在字线之下。

公开(公告)号：US5654576A

公开(公告)日：1997-08-05

申请号：US559324

申请日：1995-11-16

申请人： Chen-Chiu Hsue ,  Yi-Chung Sheng ,  Shing-Ren Sheu ,  Chen-Hui Chung

发明人： Chen-Chiu Hsue ,  Yi-Chung Sheng ,  Shing-Ren Sheu ,  Chen-Hui Chung

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L29/94

CPC分类号： H01L27/1126 ,  H01L27/112 ,  Y10S257/915

摘要： A method of manufacturing a code pattern on a semiconductor substrate with an array of substantially parallel buried bit lines integral therewith and with word lines above the buried bit lines, includes: forming a titanium nitride layer above the word lines, forming and patterning a code mask above the titanium nitride layer, implanting impurities into the substrate through openings in the code mask to form the code pattern, and performing rapid thermal annealing of the implant. The step height of the titanium nitride layer is employed to form the code identification on the substrate.

摘要翻译： 一种在半导体衬底上制造具有与其一体的基本上平行的掩埋位线阵列和掩埋位线之上的字线的阵列的方法，包括：在字线之上形成氮化钛层，形成码图掩模 在氮化钛层之上，通过编码掩模中的开口将杂质注入到衬底中，以形成编码图案，并对植入物进行快速热退火。 氮化钛层的台阶高度用于在基板上形成代码识别。