公开(公告)号：US08144516B2

公开(公告)日：2012-03-27

申请号：US12630332

申请日：2009-12-03

申请人： Yijie Zhao ,  Akira Goda ,  Jian Li ,  Haitao Liu

发明人： Yijie Zhao ,  Akira Goda ,  Jian Li ,  Haitao Liu

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C16/3418

摘要： Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for programming. If the adjacent memory cell is not programmed, the pass voltage is reduced on the adjacent memory cell. The adjacent memory cell can be on the drain side, the source side, or both drain and source sides of the selected memory cell.

摘要翻译： 公开了用于感测和存储器件的方法。 用于感测的一种这样的方法在与选定的存储器单元相邻的至少一个相邻存储器单元上使用动态通过电压用于编程。 如果相邻存储单元未编程，则相邻存储单元上的通过电压降低。 相邻的存储单元可以在所选存储单元的漏极侧，源极侧或漏极和源极侧。

公开(公告)号：US20110134697A1

公开(公告)日：2011-06-09

申请号：US12630332

申请日：2009-12-03

申请人： Yijie Zhao ,  Akira Goda ,  Jian Li ,  Haitao Liu

发明人： Yijie Zhao ,  Akira Goda ,  Jian Li ,  Haitao Liu

IPC分类号： G11C16/26 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C16/3418

摘要： Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for programming. If the adjacent memory cell is not programmed, the pass voltage is reduced on the adjacent memory cell. The adjacent memory cell can be on the drain side, the source side, or both drain and source sides of the selected memory cell.

摘要翻译： 公开了用于感测和存储器件的方法。 用于感测的一种这样的方法在与选定的存储器单元相邻的至少一个相邻存储器单元上使用动态通过电压用于编程。 如果相邻存储单元未编程，则相邻存储单元上的通过电压降低。 相邻的存储单元可以在所选存储单元的漏极侧，源极侧或漏极和源极侧。

公开(公告)号：US08102712B2

公开(公告)日：2012-01-24

申请号：US12644408

申请日：2009-12-22

申请人： Akira Goda ,  Andrew Bickler ,  Haitao Liu ,  Tomoharu Tanaka

发明人： Akira Goda ,  Andrew Bickler ,  Haitao Liu ,  Tomoharu Tanaka

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/0408 ,  G11C16/06

摘要： A NAND memory array is programmed applying a programming voltage Vpgm as a double pulse programming pulse if a data pattern associated with memory cells that are to be programmed form a two-sided column-stripe (CS2) data pattern. The CS2 data pattern comprises a memory cell that is not to be programmed directly between two memory cells that are to be programmed, such that a channel associated with the memory cell that is not to be programmed has an applied boost voltage, and the channels associated with the two memory cells that are to be programmed have an applied programming voltage. The first memory cell of the two memory cells is programmed by the first programming voltage pulse and the second memory cell is programmed by the second programming voltage pulse. A programming voltage Vpgm is applied as a single pulse if a CS2 data pattern is not formed.

摘要翻译： 如果与要编程的存储器单元相关联的数据模式形成双面列条带（CS2）数据模式，则NAND存储器阵列被编程为将编程电压Vpgm应用为双脉冲编程脉冲。 CS2数据模式包括不被直接编程在待编程的两个存储器单元之间的存储器单元，使得与不被编程的存储器单元相关联的通道具有施加的升压电压，并且所述通道相关联 要编程的两个存储单元具有应用的编程电压。 两个存储单元的第一存储单元由第一编程电压脉冲编程，第二存储单元由第二编程电压脉冲编程。 如果没有形成CS2数据模式，则将编程电压Vpgm作为单个脉冲施加。

公开(公告)号：US09171626B2

公开(公告)日：2015-10-27

申请号：US13561637

申请日：2012-07-30

申请人： Akira Goda ,  Haitao Liu ,  Krishna Parat

发明人： Akira Goda ,  Haitao Liu ,  Krishna Parat

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L27/115

CPC分类号： G11C16/10 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11582

摘要： An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.

摘要翻译： 一种方法的实施例包括在第一选择栅极截止时减小施加到第一选择栅极的电压减去施加到源极的电压的差异，减小施加到第二选择栅极的电压的差减去施加到 数据线，而第二选择栅极关闭，以及增加施加到所选择的存取线的信号的电压，该选择的存取线耦合到耦合到第一和第二选择栅极的一串存储单元中的非目标存储器单元到编程电压 之后或基本同时地减小施加到第一选择栅极的电压的差减去施加到源极的电压，并且减小施加到第二选择栅极的电压的差减去施加到数据线的电压。

公开(公告)号：US20140029345A1

公开(公告)日：2014-01-30

申请号：US13561637

申请日：2012-07-30

申请人： Akira Goda ,  Haitao Liu ,  Krishna Parat

发明人： Akira Goda ,  Haitao Liu ,  Krishna Parat

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11582

摘要： An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.

摘要翻译： 一种方法的实施例包括在第一选择栅极截止时减小施加到第一选择栅极的电压减去施加到源极的电压的差异，减小施加到第二选择栅极的电压的差减去施加到 数据线，而第二选择栅极关闭，以及增加施加到所选择的存取线的信号的电压，该选择的存取线耦合到耦合到第一和第二选择栅极的一串存储单元中的非目标存储器单元到编程电压 之后或基本同时地减小施加到第一选择栅极的电压的差减去施加到源极的电压，并且减小施加到第二选择栅极的电压的差减去施加到数据线的电压。

公开(公告)号：US20110149654A1

公开(公告)日：2011-06-23

申请号：US12644408

申请日：2009-12-22

申请人： Akira Goda ,  Andrew Bickler ,  Haitao Liu ,  Tomoharu Tanaka

发明人： Akira Goda ,  Andrew Bickler ,  Haitao Liu ,  Tomoharu Tanaka

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/0408 ,  G11C16/06

摘要： A NAND memory array is programmed applying a programming voltage Vpgm as a double pulse programming pulse if a data pattern associated with memory cells that are to be programmed form a two-sided column-stripe (CS2) data pattern. The CS2 data pattern comprises a memory cell that is not to be programmed directly between two memory cells that are to be programmed, such that a channel associated with the memory cell that is not to be programmed has an applied boost voltage, and the channels associated with the two memory cells that are to be programmed have an applied programming voltage. The first memory cell of the two memory cells is programmed by the first programming voltage pulse and the second memory cell is programmed by the second programming voltage pulse. A programming voltage Vpgm is applied as a single pulse if a CS2 data pattern is not formed.

摘要翻译： 如果与要编程的存储器单元相关联的数据模式形成双面列条带（CS2）数据模式，则NAND存储器阵列被编程为将编程电压Vpgm应用为双脉冲编程脉冲。 CS2数据模式包括不被直接编程在待编程的两个存储器单元之间的存储器单元，使得与不被编程的存储器单元相关联的通道具有施加的升压电压，并且所述通道相关联 要编程的两个存储单元具有应用的编程电压。 两个存储单元的第一存储单元由第一编程电压脉冲编程，第二存储单元由第二编程电压脉冲编程。 如果没有形成CS2数据模式，则将编程电压Vpgm作为单个脉冲施加。

公开(公告)号：US20190206889A1

公开(公告)日：2019-07-04

申请号：US15858509

申请日：2017-12-29

申请人： Akira Goda ,  Haitao Liu ,  Jin Chen ,  Guangyu Huang ,  Mojtaba Asadirad

发明人： Akira Goda ,  Haitao Liu ,  Jin Chen ,  Guangyu Huang ,  Mojtaba Asadirad

IPC分类号： H01L27/11573 ,  H01L27/11556 ,  H01L23/528 ,  H01L29/36 ,  H01L29/04 ,  H01L21/02 ,  H01L29/78 ,  H01L27/11582 ,  H01L27/11526 ,  H01L29/66 ,  H01L29/16 ,  H01L23/532 ,  G11C16/08 ,  G11C16/24

摘要： Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.

公开(公告)号：US08921891B2

公开(公告)日：2014-12-30

申请号：US13592086

申请日：2012-08-22

申请人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

发明人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

IPC分类号： H01L21/336

CPC分类号： H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

摘要翻译： 一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质 源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。 身体部分中的电介质不会沿着身体的整个长度延伸。 描述和要求保护其他实施例。

公开(公告)号：US20140054666A1

公开(公告)日：2014-02-27

申请号：US13592086

申请日：2012-08-22

申请人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

发明人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

IPC分类号： H01L29/788

CPC分类号： H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

摘要翻译： 一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质 源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。 身体部分中的电介质不会沿着身体的整个长度延伸。 描述和要求保护其他实施例。

公开(公告)号：US08431961B2

公开(公告)日：2013-04-30

申请号：US13020337

申请日：2011-02-03

申请人： Haitao Liu ,  Jian Li ,  Chandra Mouli

发明人： Haitao Liu ,  Jian Li ,  Chandra Mouli

IPC分类号： H01L29/66

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

摘要： Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

摘要翻译： 示出了包括主体区域和由具有比身体区域更低带隙的半导体形成的连接区域的存储器件。 连接区域配置可以在擦除操作期间提供增加的栅极引起的漏极泄漏。 所显示的配置可以提供用于存储器操作的身体区域的可靠偏置，例如在升压操作期间擦除和容纳身体区域中的电荷。