公开(公告)号：US06140179A

公开(公告)日：2000-10-31

申请号：US326651

申请日：1999-06-07

申请人： Yinan Chen ,  Shih-chi Hsu ,  Tse Yao Huang

发明人： Yinan Chen ,  Shih-chi Hsu ,  Tse Yao Huang

IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L21/8242

CPC分类号： H01L28/82 ,  H01L27/10814 ,  H01L28/87 ,  H01L28/91

摘要： The present invention discloses a method of forming a crown capacitor for a DRAM cell. An etching method having different selectivity between the BPSG and silicon oxynitride layer is applied to form a sacrificial structure with a concanovenex sidewall. Using the sacrificial structure as a mold, a high capacitance crown capacitor is obtained.

摘要翻译： 本发明公开了一种形成用于DRAM单元的表冠电容器的方法。 施加在BPSG和氮氧化硅层之间具有不同选择性的蚀刻方法以形成具有锥形侧壁的牺牲结构。 使用牺牲结构作为模具，获得高电容冠电容器。

公开(公告)号：US6133089A

公开(公告)日：2000-10-17

申请号：US314201

申请日：1999-05-19

申请人： Tse Yao Huang ,  Shih-Chi Hsu ,  Yinan Chen ,  Hsing-Chuan Tsai

发明人： Tse Yao Huang ,  Shih-Chi Hsu ,  Yinan Chen ,  Hsing-Chuan Tsai

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： A method for fabricating a DRAM capacitor is described. First, a semiconductor substrate having a capacitor contact is provided. Next, a first polysilicon layer is formed. Then, an oxide layer and a silicon oxy-nitride layer are sequentially formed over the first polysilicon layer. Next, the silicon oxy-nitride layer, the oxide layer, and the first polysilicon layer are selectively etched to leave a rectangular stack layer. Afterwards, the oxide layer and the first polysilicon layer of the rectangular stack layer are etched from the sidewall direction to leave a double T-shaped stack layer. Then, second polysilicon layer is formed on the upper surface and the sidewall of the double T-shaped stack layer. Next, the second polysilicon layer is selectively removed. The remaining second and first polysilicon layer are used as the bottom electrode. Afterwards, a dielectric layer and an upper electrode are formed on the bottom electrode.

摘要翻译： 描述制造DRAM电容器的方法。 首先，提供具有电容器触点的半导体衬底。 接下来，形成第一多晶硅层。 然后，在第一多晶硅层上依次形成氧化物层和氮氧化硅层。 接下来，选择性地蚀刻硅氮氧化物层，氧化物层和第一多晶硅层以留下矩形堆叠层。 然后，从侧壁方向蚀刻矩形堆叠层的氧化物层和第一多晶硅层，留下双T型堆叠层。 然后，在双T型堆叠层的上表面和侧壁上形成第二多晶硅层。 接下来，选择性地去除第二多晶硅层。 剩余的第二和第一多晶硅层用作底部电极。 之后，在底部电极上形成电介质层和上部电极。

公开(公告)号：US20060154435A1

公开(公告)日：2006-07-13

申请号：US10907101

申请日：2005-03-20

申请人： Hsiu-Chun Lee ,  Tse-Yao Huang ,  Yinan Chen

发明人： Hsiu-Chun Lee ,  Tse-Yao Huang ,  Yinan Chen

IPC分类号： H01L21/20

CPC分类号： H01L21/76232

摘要： A method of fabricating trench isolation for trench-capacitor DRAM devices. After the formation of deep trench capacitors, an isolation trench is etched into a substrate. The isolation trench is initially filled with a first insulating layer, which is then recessed into the isolation trench to a depth that is lower than the substrate main surface. An epitaxial layer is grown from the exposed sidewalls of the isolation trench. The isolation trench is then filled with a second insulating layer.

摘要翻译： 一种用于沟槽电容器DRAM器件的沟槽隔离的方法。 在形成深沟槽电容器之后，将隔离沟槽蚀刻到衬底中。 隔离沟槽最初填充有第一绝缘层，然后将第一绝缘层凹入到隔离沟槽中，其深度低于衬底主表面。 从隔离沟槽的暴露的侧壁生长外延层。 隔离沟槽然后用第二绝缘层填充。

公开(公告)号：US06909136B2

公开(公告)日：2005-06-21

申请号：US10604344

申请日：2003-07-14

申请人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Change-Rong Wu ,  Hui-Min Mao

发明人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Change-Rong Wu ,  Hui-Min Mao

IPC分类号： H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

摘要： A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

摘要翻译： 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

公开(公告)号：US20050012131A1

公开(公告)日：2005-01-20

申请号：US10604344

申请日：2003-07-14

申请人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

发明人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

IPC分类号： H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

摘要： A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

摘要翻译： 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

公开(公告)号：US09775583B2

公开(公告)日：2017-10-03

申请号：US14000632

申请日：2012-02-27

申请人： Ming Yan ,  Yinan Chen

发明人： Ming Yan ,  Yinan Chen

IPC分类号： A61B8/06 ,  A61B5/022 ,  A61B8/00 ,  A61B8/08

CPC分类号： A61B8/06 ,  A61B5/022 ,  A61B8/08 ,  A61B8/0891 ,  A61B8/42 ,  A61B8/488

摘要： The method of positioning a Doppler ultrasound transducer for performing blood flow measurement according to the invention comprises the steps of: detecting a pressure oscillation signal from an inflated cuff placed on patient's artery; detecting an ultrasound pulse signal from the Doppler ultrasound transducer placed along the artery; deriving a first signal from the pressure oscillation signal and the ultrasound pulse signal, the first signal indicating the degree of synchronization between the pressure oscillation signal and the ultrasound pulse signal; and outputting an indication signal to indicate the Doppler ultrasound transducer is in a desired position when the first signal satisfies a predefined condition. Since the synchronization property of the cuff pressure oscillation signal and the ultrasound signal caused by the blood flow is utilized to determine whether the transducer is well positioned or not, ultrasound signal, which is a pulse signal but not reflecting the blood flow of the artery, could be determined as not in synchronization with the oscillation signal and therefore the accuracy of the positioning could be improved.

公开(公告)号：US20060228845A1

公开(公告)日：2006-10-12

申请号：US11101007

申请日：2005-04-06

申请人： Yinan Chen ,  Jeng-Ping Lin ,  Feng-Chuan Lin

发明人： Yinan Chen ,  Jeng-Ping Lin ,  Feng-Chuan Lin

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/10888

摘要： Disclosed is a method for pre-retaining CB opening in a DRAM manufacture process, wherein a CB opening is filed with a photo-resist layer and an LPD oxidation layer that is filled at room temperature to avoid damaging caused by conventional etching techniques. The LPD oxidation layer and the photo-resist are replaced easily by a polysilicon layer and a BPSG layer.

公开(公告)号：US07041567B2

公开(公告)日：2006-05-09

申请号：US10904593

申请日：2004-11-18

申请人： Yinan Chen ,  Ping Hsu ,  Li-Han Lu

发明人： Yinan Chen ,  Ping Hsu ,  Li-Han Lu

IPC分类号： H01L21/461 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L21/76232 ,  H01L27/0214 ,  H01L27/10861 ,  H01L27/10867

摘要： This invention relates to a method for self-aligned fabricating an isolation structure of a trench capacitor. The method takes two steps to etch the substrate for forming the shallow trench of the isolation structure, wherein the conductive layer and the collar oxide layer of the trench capacitor remain intact during the etching processes.

摘要翻译： 本发明涉及一种用于自对准制造沟槽电容器隔离结构的方法。 该方法需要两个步骤来蚀刻用于形成隔离结构的浅沟槽的衬底，其中沟槽电容器的导电层和套环氧化物层在蚀刻工艺期间保持完整。

公开(公告)号：US20050003608A1

公开(公告)日：2005-01-06

申请号：US10610524

申请日：2003-07-02

申请人： Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yinan Chen

发明人： Ming-Cheng Chang ,  Tieh-Chiang Wu ,  Yinan Chen

IPC分类号： H01L21/225 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/78

CPC分类号： H01L27/10873 ,  H01L21/2256 ,  H01L27/10861 ,  H01L29/7834

摘要： The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The shallow trench surrounds an active area. A non-doped silicate glass (NSG) layer is deposited to fill the shallow trench, and is then etched back to a depth of the shallow trench, thereby exposing a portion of the semiconductor substrate at an upper portion of the shallow trench. A doped dielectric layer is deposited over the remaining NSG layer to cover the exposed semiconductor substrate. A thermal process is then carried out to diffuse dopants of the doped dielectric layer into the semiconductor substrate, thereby forming a doped region at the periphery of the active area in a channel width direction.

摘要翻译： 本发明提供了一种用于消除DRAM器件制造中的反窄窄度效应的方法。 在其上设置有一个浅沟槽的半导体衬底。 浅沟环绕有效区域。 沉积非掺杂硅酸盐玻璃（NSG）层以填充浅沟槽，然后将其蚀刻回浅沟槽的深度，从而将半导体衬底的一部分暴露在浅沟槽的上部。 在剩余的NSG层上沉积掺杂介电层以覆盖暴露的半导体衬底。 然后进行热处理以将掺杂介电层的掺杂剂扩散到半导体衬底中，从而在沟道宽度方向上的有源区的周边形成掺杂区。

公开(公告)号：US06797611B1

公开(公告)日：2004-09-28

申请号：US10604600

申请日：2003-08-03

申请人： Kuo-Chien Wu ,  Yinan Chen

发明人： Kuo-Chien Wu ,  Yinan Chen

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76816 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894

摘要： A method of fabricating contact holes on a semiconductor chip with a plurality of gates and a first mask layer includes filling a dielectric layer into the inter-gate space of two gates, polishing the dielectric layer until the surface of the dielectric layer is coplanar with the gates, depositing a second mask layer, etching the second mask layer to form a bit line opening in an array area and simultaneously forming a gate opening and a substrate opening in a periphery area, removing a portion of the dielectric layer through the bit line opening and the substrate opening to form a bit line contact hole and a substrate contact hole, filling a metal layer into the bit line contact hole and the substrate contact hole, and etching the first mask layer through the gate opening to form a gate contact hole.

摘要翻译： 在具有多个栅极和第一掩模层的半导体芯片上制造接触孔的方法包括将电介质层填充到两个栅极的栅极间空间中，抛光电介质层直到电介质层的表面与 栅极，沉积第二掩模层，蚀刻第二掩模层以形成在阵列区域中开口的位线，同时在周边区域形成栅极开口和基板开口，通过位线开口去除电介质层的一部分 和基板开口以形成位线接触孔和衬底接触孔，将金属层填充到位线接触孔和衬底接触孔中，并且通过栅极开口蚀刻第一掩模层以形成栅极接触孔。