公开(公告)号：US07080269B2

公开(公告)日：2006-07-18

申请号：US10439040

申请日：2003-05-15

申请人： Yoanna Baumgartner ,  Sundeep Chadha ,  Richard Nicholas Iachetta, Jr. ,  Hien Minh Le ,  Kirk Edward Morrow

发明人： Yoanna Baumgartner ,  Sundeep Chadha ,  Richard Nicholas Iachetta, Jr. ,  Hien Minh Le ,  Kirk Edward Morrow

IPC分类号： G06F1/26

CPC分类号： G06F1/3228 ,  G06F1/12 ,  G06F1/324 ,  Y02D10/126

摘要： A system and a method are provided for implementing a power-saving sleep mode in a synchronous circuit core having multiple clock domains including primary and secondary clock domains. The primary clock domain has states of awake, asleep, doze, and waking. The doze and waking states are transient states between the awake and asleep states. One or more secondary clock domains each have states of secondary awake and secondary asleep. The doze and waking states are used to eliminate race conditions between the primary and secondary clock domains. If the core has two or more secondary clock domains, the secondary clock domains each have an additional state of sleep-pending. The sleep-pending state is a transient state between the secondary awake and secondary asleep states. One or more synchronization logics are coupled between the primary and secondary clock domains.

摘要翻译： 提供了一种用于在具有包括主时钟域和次时钟域的多个时钟域的同步电路核中实现节电睡眠模式的系统和方法。 主时钟域具有清醒，睡眠，打盹和醒来的状态。 打盹和醒来的状态是唤醒和睡眠状态之间的瞬态状态。 一个或多个次级时钟域各自具有二次唤醒和次要睡眠状态。 打盹和醒来的状态被用来消除主时钟和次要时钟域之间的竞争条件。 如果核心具有两个或多个次级时钟域，则辅助时钟域各自具有待处理的附加状态。 睡眠挂起状态是二次唤醒和二次睡眠状态之间的暂态。 一个或多个同步逻辑耦合在主时钟域和次时钟域之间。

公开(公告)号：US06192452B1

公开(公告)日：2001-02-20

申请号：US09259378

申请日：1999-02-26

申请人： John Peyton Bannister ,  Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

发明人： John Peyton Bannister ,  Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G06F1200

CPC分类号： G06F12/0813

摘要： A method for avoiding data loss due to cancelled transactions within a non-uniform memory access (NUMA) data processing system is disclosed. A NUMA data processing system includes a node interconnect to which at least a first node and a second node are coupled. The first and the second nodes each includes a local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and a node interconnect. The node controller detects certain situations which, due to the nature of a NUMA data processing system, can lead to data loss. These situations share the common feature that a node controller ends up with the only copy of a modified cache line and the original transaction that requested the modified cache line may not be issued again with the same tag or may not be issued again at all. The node controller corrects these situations by issuing its own write transaction to the system memory for that modified cache line using its own tag, and then providing the data the modified cache line is holding. This ensures that the modified data will be written to the system memory.

摘要翻译： 公开了一种用于避免由于在非均匀存储器访问（NUMA）数据处理系统中被取消的事务而导致的数据丢失的方法。 NUMA数据处理系统包括至少第一节点和第二节点耦合到的节点互连。 第一和第二节点各自包括本地互连，耦合到本地互连的系统存储器和插入在本地互连和节点互连之间的节点控制器。 节点控制器检测某些情况，由于NUMA数据处理系统的性质，可能导致数据丢失。 这些情况共享了节点控制器以修改的高速缓存行的唯一副本结束的共同特征，并且请求修改的高速缓存行的原始事务可能不会以相同的标签重新发出，也可能根本不再发出。 节点控制器通过使用其自己的标签向修改的高速缓存行发出自己的写入事务来修正这些情况，然后提供修改后的高速缓存行正在保存的数据。 这样可以确保将修改后的数据写入系统内存。

公开(公告)号：US6055600A

公开(公告)日：2000-04-25

申请号：US772046

申请日：1996-12-19

申请人： Thoi Nguyen ,  Richard Nicholas Iachetta, Jr. ,  Yashwant Sakarchand Kothari ,  Allan Rowe Steel ,  Keith Alan Cox

发明人： Thoi Nguyen ,  Richard Nicholas Iachetta, Jr. ,  Yashwant Sakarchand Kothari ,  Allan Rowe Steel ,  Keith Alan Cox

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0897

摘要： A method and apparatus for detecting and identifying the attributes of level-2 (L2) memory cache modules in a computer system. An ID Module is attached to each L2 cache memory module containing memory attribute information such as size, presence or absence of parity, synchronous or asynchronous access ability, electrical timing, etc. The information is accessible using a parallel or serial interface.

摘要翻译： 一种用于在计算机系统中检测和识别级别2（L2）存储器高速缓存模块的属性的方法和装置。 ID模块连接到每个L2高速缓冲存储器模块，其中包含存储器属性信息，如大小，存在或不存在奇偶校验，同步或异步访问能力，电时间等。该信息可使用并行或串行接口访问。

公开(公告)号：US6081874A

公开(公告)日：2000-06-27

申请号：US162828

申请日：1998-09-29

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G06F15/163 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0813

摘要： A non-uniform memory access (NUMA) data processing system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the request transaction should be processed at the second processing node.

摘要翻译： 非均匀存储器访问（NUMA）数据处理系统包括至少第一处理节点和第二处理节点耦合到的节点互连。 第一处理节点和第二处理节点各自包括本地互连，耦合到本地互连的处理器，耦合到本地互连的系统存储器，以及插入在本地互连和节点互连之间的节点控制器。 为了减少通信延迟，第一处理节点的节点控制器通过节点互连将从第一处理节点的本地互连接收的请求事务推测发送到第二处理节点。 在一个实施例中，第一处理节点的节点控制器随后将状态信号发送到第二处理节点的节点控制器，以便指示如何在第二处理节点处理请求事务。

公开(公告)号：US06973520B2

公开(公告)日：2005-12-06

申请号：US10195172

申请日：2002-07-11

申请人： Bernard Charles Drerup ,  Jaya Prakash Subramaniam Ganasan ,  Richard Gerard Hofmann ,  Richard Nicholas Iachetta, Jr. ,  Barry Joe Wolford

发明人： Bernard Charles Drerup ,  Jaya Prakash Subramaniam Ganasan ,  Richard Gerard Hofmann ,  Richard Nicholas Iachetta, Jr. ,  Barry Joe Wolford

IPC分类号： G06F13/00 ,  G06F13/14 ,  G06F13/364

CPC分类号： G06F13/364

摘要： An electronic system is disclosed, including multiple initiators and one or more targets coupled to a bus, and a request mask control unit (RMCU). The initiators are configured to initiate requests (e.g., read requests and write requests) via the bus, and the targets are configured to receive requests from the initiators via the bus. The targets are also configured to produce multiple MaskEnable signals, wherein each of the MaskEnable signals is generated following an initial request received via the bus, and dependent on a corresponding “masking situation” within the target. The RMCU receives the MaskEnable signals and produces multiple RequestMask signals dependent upon the MaskEnable signals. One or more of the initiators are permitted to repeat requests via the bus dependent upon one or more of the RequestMask signals. This mechanism provides additional bus bandwidth for carrying out successful data transfers.

摘要翻译： 公开了一种电子系统，包括多个启动器和耦合到总线的一个或多个目标，以及请求掩码控制单元（RMCU）。 启动器被配置为经由总线发起请求（例如，读请求和写请求），并且目标被配置为经由总线接收来自发起者的请求。 目标还被配置为产生多个MaskEnable信号，其中每个MaskEnable信号是在经由总线接收到的初始请求之后生成的，并且取决于目标内相应的“屏蔽情况”。 RMCU接收MaskEnable信号，并根据MaskEnable信号产生多个RequestMask信号。 一个或多个启动器被允许经由总线重复请求，取决于一个或多个请求掩码信号。 该机制为进行成功的数据传输提供了额外的总线带宽。

公开(公告)号：US06178472B1

公开(公告)日：2001-01-23

申请号：US09097331

申请日：1998-06-15

申请人： Gary Dale Carpenter ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

发明人： Gary Dale Carpenter ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G06F1312

CPC分类号： G06F7/78

摘要： A queue includes a data multiplexer having an output and at least two inputs and a plurality of data latches. The data latches include at least a first data latch and a second data latch, which each have a data input and a data output. The data output of the first data latch is coupled to a first input of the data multiplexer, and the output of the data multiplexer is coupled to the data input of the second data latch. A data value to be stored in the queue is received at a second input to the data multiplexer. In response to one or more control signals, the data value is latched into at least one of the first and second data latches, thereby storing the data value in the queue. Depending upon the design of the control logic, the queue can implement either first in, first out (FIFO) or last in, first out (LIFO) behavior.

摘要翻译： 队列包括具有输出和至少两个输入和多个数据锁存器的数据多路复用器。 数据锁存器至少包括第一数据锁存器和第二数据锁存器，每个锁存器具有数据输入和数据输出。 第一数据锁存器的数据输出耦合到数据多路复用器的第一输入端，并且数据多路复用器的输出耦合到第二数据锁存器的数据输入端。 要存储在队列中的数据值在第二输入处被接收到数据多路复用器。 响应于一个或多个控制信号，数据值被锁存到第一和第二数据锁存器中的至少一个中，从而将数据值存储在队列中。 根据控制逻辑的设计，队列可以先进先出（FIFO）或最后进先出（LIFO）行为。

公开(公告)号：US6085293A

公开(公告)日：2000-07-04

申请号：US135283

申请日：1998-08-17

申请人： Gary Dale Carpenter ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

发明人： Gary Dale Carpenter ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G06F15/16 ,  G06F12/08 ,  G06F12/16

CPC分类号： G06F12/0813 ,  G06F2212/2542

摘要： A non-uniform memory access (NUMA) computer system includes a node interconnect and a plurality of processing nodes that each contain at least one processor, a local interconnect, a local system memory, and a node controller coupled to both a respective local interconnect and the node interconnect. According to the method of the present invention, a communication transaction is transmitted on the node interconnect from a local processing node to a remote processing node. In response to receipt of the communication transaction by the remote processing node, a response including a coherency response field is transmitted on the node interconnect from the remote processing node to the local processing node. In response to receipt of the response at the local processing node, a request is issued on the local interconnect of the local processing node concurrently with a determination of a coherency response indicated by the coherency response field.

摘要翻译： 不均匀存储器访问（NUMA）计算机系统包括节点互连和多个处理节点，每个处理节点包含至少一个处理器，本地互连，本地系统存储器和耦合到相应的本地互连和 节点互连。 根据本发明的方法，在节点互连上从本地处理节点向远程处理节点发送通信事务。 响应于远程处理节点接收到通信事务，在节点互连上从远程处理节点向本地处理节点发送包括一致性响应字段的响应。 响应于在本地处理节点处的响应的接收，在本地处理节点的本地互连上同时确定由相关性响应字段指示的一致性响应的请求。

公开(公告)号：US06829677B1

公开(公告)日：2004-12-07

申请号：US09574186

申请日：2000-05-18

申请人： David Lawrence Attaway ,  Leonard F. Chetti ,  Richard Nicholas Iachetta, Jr. ,  Suksoon Yong

发明人： David Lawrence Attaway ,  Leonard F. Chetti ,  Richard Nicholas Iachetta, Jr. ,  Suksoon Yong

IPC分类号： G06F1200

CPC分类号： G11C11/4072 ,  G11C7/20 ,  G11C8/10 ,  G11C11/406 ,  G11C11/40615

摘要： A method, system, and apparatus for maintaining the contents of a self-refreshable memory device during periods of data processing system reset is provided. In one embodiment, a refresh controller receives an indication that the data processing system is being reset. If necessary, the refresh controller modifies the signal from a memory controller to the memory device such that the memory device is placed in a self-refresh mode. The refresh controller keeps the memory device in the self-refresh mode until the data processing system re-enables external refresh signals.

摘要翻译： 提供了一种用于在数据处理系统复位期间维持自刷新存储器件的内容的方法，系统和装置。 在一个实施例中，刷新控制器接收数据处理系统正被重置的指示。 如果需要，刷新控制器将来自存储器控制器的信号修改为存储器件，使得存储器件被置于自刷新模式。 刷新控制器保持存储器件处于自刷新模式，直到数据处理系统重新启用外部刷新信号。

公开(公告)号：US06801977B2

公开(公告)日：2004-10-05

申请号：US10042096

申请日：2002-01-07

申请人： Bernard Charles Drerup ,  Richard Nicholas Iachetta, Jr.

发明人： Bernard Charles Drerup ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G07F1336

CPC分类号： G06F13/4059

摘要： An apparatus and method for passing messages through a bus-to-bus bridge while maintaining ordering. The method comprises passing messages into a message container in the bus bridge without using the bridge buffer, setting a flag that tracks all the writes in the write queue ahead of when the message was put into the message container, blocking the receiving device on the bus connected to the bridge from accessing the message container until the flag is cleared, and clearing the flag when all the writes put into the write queue ahead of when the flag was set have been written to local memory on the receiving bus, then allowing the device on the receiving bus that is the intended recipient to receive the message.

摘要翻译： 一种用于在保持排序的同时通过总线到总线桥接信息的装置和方法。 该方法包括将消息传递到总线桥中的消息容器中，而不使用桥接缓冲器，设置在消息被放入消息容器之前跟踪写入队列中的所有写入的标志，阻止总线上的接收设备 连接到桥接器访问消息容器直到标志被清除，并且当在设置标志之后写入队列的所有写入已经被写入到接收总线上的本地存储器中时清除标志，然后允许该设备 在接收消息的接收总线上。

公开(公告)号：US5867037A

公开(公告)日：1999-02-02

申请号：US736303

申请日：1996-10-24

申请人： Louis Bennie Capps, Jr. ,  Richard Nicholas Iachetta, Jr. ,  An Xuan Tra

发明人： Louis Bennie Capps, Jr. ,  Richard Nicholas Iachetta, Jr. ,  An Xuan Tra

IPC分类号： G06F17/50 ,  H03K19/173

CPC分类号： G06F17/5054

摘要： A method and apparatus for receiving and transmitting programming data through an application specific integrated circuit is provided. In a first embodiment, the application specific integrated circuit comprises a main circuit, at least two input/output (I/O) mechanisms connected to the main circuit for transferring data into and out of the main circuit and a mechanism for receiving and transmitting the programming data. The mechanism for transmitting the programming data includes a tri-state buffer that is activated by a programming enable signal. In a second embodiment, the input and output of the buffer are multiplexed with the two I/O mechanisms connected to the main circuit.

摘要翻译： 提供了一种通过专用集成电路接收和发送编程数据的方法和装置。 在第一实施例中，专用集成电路包括主电路，连接到主电路的用于将数据传入和传出主电路的至少两个输入/输出（I / O）机构，以及用于接收和发送 编程数据。 用于发送编程数据的机制包括由编程使能信号激活的三态缓冲器。 在第二实施例中，缓冲器的输入和输出与连接到主电路的两个I / O机构复用。