Multiphase synchronous buck converter
    7.
    发明授权
    Multiphase synchronous buck converter 有权
    多相同步降压转换器

    公开(公告)号:US07696612B2

    公开(公告)日:2010-04-13

    申请号:US12020892

    申请日:2008-01-28

    IPC分类号: H01L23/495

    摘要: Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dies and at least nine parallel leads. The dies are electrically connected through a plurality of die attach pads, thus eliminating the need for wirebonding.

    摘要翻译: 在本说明书中公开了一种用于形成这种封装的多相降压转换器封装和工艺。 该封装包括至少四个裸片和至少九个平行引线。 模具通过多个管芯附接焊盘电连接,因此不需要引线接合。

    Thin Compact Semiconductor Die Packages Suitable for Smart-Power Modules, Methods of Making the Same, and Systems Using the Same
    8.
    发明申请
    Thin Compact Semiconductor Die Packages Suitable for Smart-Power Modules, Methods of Making the Same, and Systems Using the Same 审中-公开
    适用于智能功率模块的薄型紧凑型半导体模具封装,使用该模块的方法和使用它的系统

    公开(公告)号:US20090194857A1

    公开(公告)日:2009-08-06

    申请号:US12024847

    申请日:2008-02-01

    IPC分类号: H01L23/495 H01L21/00

    摘要: Disclosed are semiconductor die packages, methods of making them, and systems incorporating them. An exemplary package comprises a first substrate, a second substrate, a semiconductor die disposed between the first and second substrates, and an electrically conductive member disposed between the first and second substrates. The semiconductor die has a conductive region at its first surface that is electrically coupled to a first conductive region of the first substrate, and another conductive region at its second surface that is electrically coupled to a first conductive region of the second substrate. The conductive member is electrically coupled between the first conductive region of the second substrate and a second electrically conductive region of the first substrate. This configuration enables terminals on both surfaces of the semiconductor die to be coupled to the first substrate.

    摘要翻译: 公开了半导体管芯封装,制造方法以及结合它们的系统。 示例性封装包括第一衬底,第二衬底,设置在第一和第二衬底之间的半导体管芯,以及设置在第一和第二衬底之间的导电构件。 半导体管芯在其第一表面处具有电耦合到第一衬底的第一导电区域的导电区域,以及在其第二表面处的电耦合到第二衬底的第一导电区域的另一导电区域。 导电构件电耦合在第二基板的第一导电区域和第一基板的第二导电区域之间。 这种配置使得半导体管芯的两个表面上的端子能够耦合到第一基板。