公开(公告)号：US20080191288A1

公开(公告)日：2008-08-14

申请号：US12030118

申请日：2008-02-12

申请人： Yong-Hyun KWON ,  Jae-Seung HWANG ,  Jun SEO ,  Sung-Il CHO ,  Sang-Joon PARK ,  Eun-Young KANG ,  Hyun-Chul KIM ,  Jung-Hoon CHAE

发明人： Yong-Hyun KWON ,  Jae-Seung HWANG ,  Jun SEO ,  Sung-Il CHO ,  Sang-Joon PARK ,  Eun-Young KANG ,  Hyun-Chul KIM ,  Jung-Hoon CHAE

IPC分类号： H01L21/336

CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/4236

摘要： In a semiconductor device including a transistor having an embedded gate, and methods of manufacturing the same, a substrate is divided into first and second regions. A gate trench is formed in the first region, a first gate structure partially fills the gate trench and a passivation layer pattern is provided inside the gate trench and positioned on the first gate structure. A first source/drain is provided adjacent to sidewalls of the first gate structure. A second gate structure is provided in the second region and has a silicon oxide layer, a conductive layer pattern and a metal silicide layer pattern stacked on the conductive layer pattern. A second source/drain is provided adjacent to sidewalls of the second gate structure. Defects due to formation of reactants may be reduced in a formation process of the above-described semiconductor device, improving reliability and operating characteristics.

摘要翻译： 在包括具有嵌入栅极的晶体管的半导体器件及其制造方法中，衬底被分成第一和第二区域。 栅极沟槽形成在第一区域中，第一栅极结构部分地填充栅极沟槽，并且钝化层图案设置在栅极沟槽内并且位于第一栅极结构上。 在第一栅极结构的侧壁附近提供第一源极/漏极。 第二栅极结构设置在第二区域中，并且具有堆叠在导电层图案上的氧化硅层，导电层图案和金属硅化物层图案。 在第二栅极结构的侧壁附近提供第二源极/漏极。 在上述半导体器件的形成过程中可能会减少由于反应物的形成而导致的缺陷，提高了可靠性和操作特性。

公开(公告)号：US20090011590A1

公开(公告)日：2009-01-08

申请号：US12136626

申请日：2008-06-10

申请人： Yong-Hwan RYU ,  Jun SEO ,  Eun-Young KANG ,  Jae-Seung HWANG ,  Sung-Un KWON

发明人： Yong-Hwan RYU ,  Jun SEO ,  Eun-Young KANG ,  Jae-Seung HWANG ,  Sung-Un KWON

IPC分类号： H01L21/4763

CPC分类号： H01L23/535 ,  H01L21/743 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.

摘要翻译： 提供一种制造半导体器件的方法，其中可以形成具有细间距和均匀厚度的多条导线。 该方法包括在绝缘层中形成多个第一导电图案作为闭合曲线，在绝缘层上形成多个掩模图案，掩模图案暴露出每个第一导电图案的端部，并且形成多个第二导电 通过去除每个第一导电图案的端部，将绝缘层中的图案作为线。

公开(公告)号：US20070287287A1

公开(公告)日：2007-12-13

申请号：US11759788

申请日：2007-06-07

申请人： Yun-Seung KANG ,  Jun SEO ,  Min-Chul CHAE ,  Jae-Seung HWANG ,  Sung-Un KWON ,  Woo-Jin CHO

发明人： Yun-Seung KANG ,  Jun SEO ,  Min-Chul CHAE ,  Jae-Seung HWANG ,  Sung-Un KWON ,  Woo-Jin CHO

IPC分类号： H01L21/44

CPC分类号： H01L27/11551 ,  H01L21/31144 ,  H01L21/743 ,  H01L27/0688 ,  H01L27/11526

摘要： Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.

摘要翻译： 提供一种制造具有高纵横比的接触孔的半导体器件的方法。 该方法包括：在半导体衬底上依次形成下图案和上层; 在上层依次形成下掩模层和上掩模层; 顺序地图案化上下掩模层以形成暴露下图案上的上层的顶表面的孔; 使用上掩模层作为蚀刻掩模以各向异性地蚀刻暴露的顶表面以形成暴露下图案的顶表面的上接触孔; 并且使用下掩模层作为蚀刻掩模来各向异性蚀刻暴露的下图案以在下图案中形成下接触孔，下接触孔从上接触孔延伸。

公开(公告)号：US20130260568A1

公开(公告)日：2013-10-03

申请号：US13569586

申请日：2012-08-08

申请人： Jae Seung HWANG ,  Jae-Won LEE ,  Jun SEO

发明人： Jae Seung HWANG ,  Jae-Won LEE ,  Jun SEO

IPC分类号： H01L21/308

CPC分类号： H01L21/32135 ,  H01L21/32139 ,  H01L27/1288

摘要： A manufacturing method for a thin film transistor array panel includes: providing a gate line including a gate electrode, on a substrate; providing a gate insulating layer covering the gate line; providing a semiconductor material layer on the gate insulating layer; providing a data wire material layer on the semiconductor material layer; providing a first photosensitive film pattern on the data wire material layer; etching the data wire material layer by using the first photosensitive film pattern as a mask; providing a second photosensitive film pattern by etching back the first photosensitive film pattern; etching the semiconductor material layer by using the second photosensitive film pattern as a mask; and etching the data wire material layer by using the second photosensitive film pattern as a mask to form a source electrode and a drain electrode. The etching the semiconductor material layer uses a first non-sulfur fluorinated gas.

摘要翻译： 薄膜晶体管阵列板的制造方法包括：在基板上设置包括栅电极的栅极线; 提供覆盖所述栅极线的栅极绝缘层; 在栅绝缘层上提供半导体材料层; 在半导体材料层上提供数据线材料层; 在数据线材料层上提供第一感光膜图案; 通过使用第一感光膜图案作为掩模来蚀刻数据线材层; 通过蚀刻第一感光膜图案提供第二感光膜图案; 通过使用第二感光膜图案作为掩模蚀刻半导体材料层; 并通过使用第二感光膜图案作为掩模来蚀刻数据线材层，以形成源电极和漏电极。 半导体材料层的蚀刻使用第一非硫氟化气体。

公开(公告)号：US20080124871A1

公开(公告)日：2008-05-29

申请号：US11773372

申请日：2007-07-03

申请人： Jun SEO ,  Jong-Heui SONG ,  Jae-Seung HWANG ,  Min-Chul CHAE ,  Woo-Jin CHO ,  Yun-Seung KANG ,  Young-Mi LEE

发明人： Jun SEO ,  Jong-Heui SONG ,  Jae-Seung HWANG ,  Min-Chul CHAE ,  Woo-Jin CHO ,  Yun-Seung KANG ,  Young-Mi LEE

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.

摘要翻译： 一种制造包括鳍状场效应晶体管（Fin-FET）的半导体器件的方法包括：在半导体衬底上形成牺牲棒，对牺牲棒进行构图以在半导体衬底上形成牺牲岛，形成器件隔离层以填充第 牺牲岛，选择性地去除牺牲岛以将牺牲岛下方的半导体衬底暴露出来，并且使用器件隔离层作为蚀刻掩模来各向异性蚀刻暴露的半导体衬底以形成凹陷沟道区。 凹陷沟道区域允许晶体管的沟道宽度和沟道长度增加，从而减少在高度集成的半导体器件中的短沟道效应和窄沟道效应的发生。

公开(公告)号：US20080090356A1

公开(公告)日：2008-04-17

申请号：US11956153

申请日：2007-12-13

申请人： Jong-Chul PARK ,  Jun SEO ,  Tae-Hyuk AHN ,  Hyuk-Jin KWON ,  Jong-Heui SONG ,  Dae-Keun KANG

发明人： Jong-Chul PARK ,  Jun SEO ,  Tae-Hyuk AHN ,  Hyuk-Jin KWON ,  Jong-Heui SONG ,  Dae-Keun KANG

IPC分类号： H01L21/336

CPC分类号： H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

摘要： A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.

摘要翻译： 根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域，形成掩模图案，其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域 使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域，以凹陷到第一深度，蚀刻沟道子区域以形成栅极沟槽，栅极沟道具有第二 深度比使用掩模图案的第一深度深的蚀刻掩模，以及形成填充栅极沟槽的凹槽。

公开(公告)号：US20070190734A1

公开(公告)日：2007-08-16

申请号：US11735919

申请日：2007-04-16

申请人： Hyeoung-Won SEO ,  Nak-Jin SON ,  Du-Heon SONG ,  Jun SEO

发明人： Hyeoung-Won SEO ,  Nak-Jin SON ,  Du-Heon SONG ,  Jun SEO

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L29/78 ,  Y10S438/942

摘要： According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.

摘要翻译： 根据本发明的一些实施例，一种方法包括制备具有有源区的半导体衬底，在有源区中掺杂沟道离子，在掺杂有沟道的有源区的预定区域中形成平面化选择性外延生长（SEG）层 离子，在具有平坦化SEG层的半导体衬底上依次形成栅极绝缘层，栅极导电层和栅极硬掩模层，通过顺序构图栅极硬掩模层和栅极导电层形成与有源区交叉的栅极图案 ，平面化SEG层位于栅极图案的一侧，并且通过使用栅极图案作为离子注入掩模注入杂质离子来形成源极/漏极区域。 因此，提供了一种不对称源/漏晶体管，其能够通过将沟道离子扩散到SEG层中来防止漏电流。

公开(公告)号：US20090237980A1

公开(公告)日：2009-09-24

申请号：US12392780

申请日：2009-02-25

申请人： Min-Sang KIM ,  Ji-Myoung LEE ,  Hyun-Jun BAE ,  Dong-Won KIM ,  Jun SEO ,  Weonwi JANG ,  Keun-Hwi CHO

发明人： Min-Sang KIM ,  Ji-Myoung LEE ,  Hyun-Jun BAE ,  Dong-Won KIM ,  Jun SEO ,  Weonwi JANG ,  Keun-Hwi CHO

IPC分类号： G11C11/24 ,  G11C11/00 ,  G11C11/416

CPC分类号： H01L28/40 ,  H01L27/10894

摘要： A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.

摘要翻译： 存储装置包括存储节点，第一电极和形成在存储单元中的第二电极，所述存储节点存储电荷，所述第一电极包括电连接到第二部分的第一部分，所述第一部分移动以连接到 当第二电极通电时的存储节点。