公开(公告)号：US08871591B2

公开(公告)日：2014-10-28

申请号：US13600025

申请日：2012-08-30

申请人： Yong-Hyun Kwon ,  Dae-Hyun Jang ,  Seong-Soo Lee ,  Kyoung-Sub Shin

发明人： Yong-Hyun Kwon ,  Dae-Hyun Jang ,  Seong-Soo Lee ,  Kyoung-Sub Shin

IPC分类号： H01L21/336

CPC分类号： H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.

摘要翻译： 根据本发明构思的示例性实施例，一种方法包括在基板上的单元图案之间形成单元图案和绝缘夹层。 在最上面的单元图案上形成包括初始接触孔和预接触孔的上绝缘层。 形成第一反射限制层图案和第一光致抗蚀剂层图案，用于暴露第一初步接触孔，同时覆盖初始和初步接触孔的入口部分。 在第一初步接触孔下方的层上进行第一蚀刻处理，以在比第一预接触孔的底部低的位置处露出电池图案。 重复第一反射限制层图案和第一光致抗蚀剂层图案的侧壁部分的部分去除处理以及通过预接触孔的底部的暴露层上的蚀刻工艺，以形成具有不同深度的接触孔。

公开(公告)号：US08557661B2

公开(公告)日：2013-10-15

申请号：US13314627

申请日：2011-12-08

申请人： Han-Geun Yu ,  Gyung-Jin Min ,  Seong-Soo Lee ,  Suk-Ho Joo ,  Yoo-Chul Kong ,  Dae-Hyun Jang

发明人： Han-Geun Yu ,  Gyung-Jin Min ,  Seong-Soo Lee ,  Suk-Ho Joo ,  Yoo-Chul Kong ,  Dae-Hyun Jang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11565 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11575 ,  H01L27/11582

摘要： A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.

摘要翻译： 一种制造半导体器件的方法包括在存储单元区域上形成存储单元，在连接区域上交替地形成牺牲层和绝缘中间层，以提供配置为电连接存储单元的布线，形成包括蚀刻掩模图案 在顶部牺牲层上的元件，在每个蚀刻掩模图案元件的每个侧壁上形成阻挡侧壁，形成第一光致抗蚀剂图案，选择性地将第一阻挡侧壁从存储器单元区域最远地覆盖并覆盖其它阻挡侧壁，蚀刻暴露顶部 牺牲层和绝缘中间层以暴露第二牺牲层，通过横向去除第一光致抗蚀剂图案至第二阻挡侧壁暴露的程度形成第二光致抗蚀剂图案，并将暴露的顶部和第二牺牲层和绝缘夹层蚀刻到 形成一个楼梯形状 d侧边缘部分。

公开(公告)号：US09048193B2

公开(公告)日：2015-06-02

申请号：US13910734

申请日：2013-06-05

申请人： Jung-Ik Oh ,  Dae-Hyun Jang ,  Seong-Soo Lee ,  Han-Na Cho

发明人： Jung-Ik Oh ,  Dae-Hyun Jang ,  Seong-Soo Lee ,  Han-Na Cho

IPC分类号： H01L21/44 ,  H01L21/308 ,  H01L21/768 ,  H01L21/311 ,  H01L27/115 ,  H01L21/027

CPC分类号： H01L21/308 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76838 ,  H01L21/76885 ,  H01L27/11575 ,  H01L27/11582

摘要： A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.

摘要翻译： 形成多层台阶图案结构的方法包括在基板上形成具有交替的绝缘夹层和牺牲层的堆叠结构。 第一光致抗蚀剂图案形成在堆叠结构上。 通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻层叠结构的部分来形成第一预备步骤图案结构。 钝化层图案形成在第一光致抗蚀剂图案和第一初步步骤图案结构的上表面上。 通过去除由钝化层图案暴露的第一光致抗蚀剂图案的侧壁部分形成第二光致抗蚀剂图案。 通过使用第二光致抗蚀剂图案作为蚀刻掩模蚀刻暴露的绝缘夹层和下面的牺牲层来形成第二初步步骤图案结构。 可以在第二预备步骤图案结构上重复上述步骤以形成多层台阶图案结构。

公开(公告)号：US20060170503A1

公开(公告)日：2006-08-03

申请号：US11323744

申请日：2005-12-30

申请人： Jae-Sup Lee ,  Hyun-Il Kang ,  Seong-Soo Lee ,  Holger Lothar ,  Ju-Hyun Ko ,  Dong-Hyun Baek ,  Song-Cheol Hong

发明人： Jae-Sup Lee ,  Hyun-Il Kang ,  Seong-Soo Lee ,  Holger Lothar ,  Ju-Hyun Ko ,  Dong-Hyun Baek ,  Song-Cheol Hong

IPC分类号： H03F3/14

CPC分类号： H03F3/604 ,  H03F1/02 ,  H03F1/22 ,  H03F3/195 ,  H03F3/265 ,  H03F2200/537 ,  H03F2200/541

摘要： A small-sized on-chip complementary metal-oxide semiconductor (CMOS) Power Amplifier having improved efficiency is provided herein. The on-chip CMOS power amplifier is capable of improving efficiency and maximizing output thereof by enhancing a K factor, which may cause a problem in a power amplifier having a distributed active transformer structure. The on-chip CMOS power amplifier having an improved efficiency and being fabricated in a small size, the on-chip CMOS power amplifier includes a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding, and a cross section for coupling the second windings with each other.

摘要翻译： 本文提供了具有提高的效率的小尺寸片上互补金属氧化物半导体（CMOS）功率放大器。 片上CMOS功率放大器能够通过增强K因子来提高效率并使其输出最大化，这可能导致具有分布式有源变压器结构的功率放大器的问题。 片上CMOS功率放大器具有改进的效率并以小尺寸制造，片上CMOS功率放大器包括位于第一层的初级绕组，位于第二层的次级绕组，其位于第二层的上部 第一层，次级绕组对应于初级绕组的位置，以及用于将第二绕组彼此联接的横截面。

公开(公告)号：US06614328B2

公开(公告)日：2003-09-02

申请号：US10080512

申请日：2002-02-25

申请人： Mi-Hyun Son ,  Seong-Soo Lee

发明人： Mi-Hyun Son ,  Seong-Soo Lee

IPC分类号： H01P120

CPC分类号： H01P1/20336

摘要： Disclosed is a radio frequency filter of a combline structure including a frequency cut-off circuit for cutting off a specific frequency from a frequency band having a given frequency bandwidth. The frequency cut-off circuit includes an inductive transmission line extending from the output terminal by a length determined to provide an approximate inductance corresponding to a calculated value approximate to an inductance for obtaining the specific frequency, and a capacitive element coupled to the approximate inductance provided by the inductive transmission line, so that it has a capacitance for obtaining the specific frequency. The inductive transmission line is connected to the capacitive element through a via hole formed at an end of the transmission line opposite to the output terminal, from which the transmission line extends. The invention also proposes a method for implementing the radio frequency filter.

公开(公告)号：US07379844B2

公开(公告)日：2008-05-27

申请号：US11276127

申请日：2006-02-15

申请人： Suk-Han Lee ,  Seong-Soo Lee ,  Jang-Yong Lee ,  Seung-Min Baek

发明人： Suk-Han Lee ,  Seong-Soo Lee ,  Jang-Yong Lee ,  Seung-Min Baek

IPC分类号： G06F15/00 ,  G06F7/60

CPC分类号： G05B13/04 ,  G05B17/02

摘要： Disclosed is a technique for obtaining an estimate and variance of each variable based on a constraint manifold. Particles (or samples) are sampled in order to filter and fuse ambiguous data or information on at least one state variable of a system using the particles. The sampling is carried out in consideration of an influence which non-linearity of the constraint manifold of a system model, an observation model or another system model exerts on a probability distribution of the state variable. With this construction, it is possible to reduce decrease of fusion and filtering performance, decrease a Gaussian approximation error, and detect mismatched information.

摘要翻译： 公开了一种基于约束歧管获得每个变量的估计和方差的技术。 对粒子（或样本）进行采样，以便使用粒子对系统的至少一个状态变量进行过滤和融合不明确的数据或信息。 考虑到系统模型，观测模型或其他系统模型的约束歧管的非线性对状态变量的概率分布施加的影响来进行抽样。 利用这种结构，可以减少融合和滤波性能的降低，降低高斯近似误差，并检测不匹配的信息。

公开(公告)号：US20050245225A1

公开(公告)日：2005-11-03

申请号：US11089219

申请日：2005-03-24

申请人： Yun-Seo Park ,  Sang-Hyun Woo ,  Hwan-Seok Song ,  Seong-Soo Lee ,  Chang-Ho Lee ,  Joy Laskar

发明人： Yun-Seo Park ,  Sang-Hyun Woo ,  Hwan-Seok Song ,  Seong-Soo Lee ,  Chang-Ho Lee ,  Joy Laskar

IPC分类号： H04B1/40 ,  H03D7/16 ,  H03H7/20 ,  H03H7/21 ,  H04B1/16 ,  H04B1/26 ,  H04B15/00

CPC分类号： H03D7/165 ,  H03H7/20 ,  H03H7/21 ,  H03H2007/0192

摘要： An apparatus for generating an in-phase/quadrature-phase (I/Q) signal in a wireless transceiver is disclosed, including a local oscillator for generating a local oscillation signal, and first and second mixers for mixing the oscillation signal with a transmission/reception signal to convert the transmission/reception signal into a baseband or high-frequency signal. The apparatus includes a phase locked circuit for controlling the local oscillator, and a polyphase filter installed between the local oscillator and the mixers, for separating the oscillation signal from the local oscillator into an I signal and a Q signal depending on a control signal from the phase locked circuit, and outputting the separated I and Q signals to the first and second mixers, respectively.

摘要翻译： 公开了一种用于在无线收发机中产生同相/正交相（I / Q）信号的装置，包括用于产生本地振荡信号的本地振荡器，以及用于将振荡信号与发送/ 接收信号将发送/接收信号转换为基带或高频信号。 该装置包括用于控制本地振荡器的锁相电路和安装在本地振荡器和混频器之间的多相滤波器，用于根据来自该振荡器的控制信号将振荡信号与本地振荡器分离成I信号和Q信号 并且将分离的I和Q信号分别输出到第一和第二混频器。

公开(公告)号：US20050225371A1

公开(公告)日：2005-10-13

申请号：US11082537

申请日：2005-03-17

申请人： Young-Hwan Kim ,  Seong-Soo Lee ,  Hak-Sun Kim ,  Chang-Seok Lee ,  Soo-Yong Park ,  Yu-Sin Kim

发明人： Young-Hwan Kim ,  Seong-Soo Lee ,  Hak-Sun Kim ,  Chang-Seok Lee ,  Soo-Yong Park ,  Yu-Sin Kim

IPC分类号： H03K3/017 ,  A61N1/18 ,  H03K5/06

CPC分类号： H03K5/06

摘要： An impulse generation circuit is provided for generating an impulse using a transmission line. Impulse characteristics of the impulse generation circuit are varied with the length of a transmission line rather than the characteristic variation of various devices used therein. The length of the transmission line is adjusted, such that a width of a generated pulse is adjusted. Because an end of the transmission line is short-circuited, the transmission line length can be easily adjusted on a substrate, and a ringing phenomenon due to re-reflection can be removed using termination impedance.

摘要翻译： 提供脉冲发生电路，用于使用传输线产生脉冲。 脉冲发生电路的脉冲特性随着传输线的长度而不同于其中使用的各种装置的特性变化而变化。 调整传输线的长度，使得产生的脉冲的宽度被调整。 由于传输线的一端短路，因此可以在基板上容易地调整传输线路长度，并且可以使用终端阻抗来消除由于再反射引起的振铃现象。

公开(公告)号：US07348676B2

公开(公告)日：2008-03-25

申请号：US11149600

申请日：2005-06-09

申请人： Seong-Soo Lee

发明人： Seong-Soo Lee

IPC分类号： H01L23/48

CPC分类号： H01L21/76877 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： After an insulation layer is formed on a substrate, a contact hole is formed through the insulation layer. A recessed plug is formed to partially fill up the contact hole. The recessed plug has a height substantially smaller than a depth of the contact hole. A metal wiring structure is formed on the recessed plug and on the insulation layer. A lower portion of the metal wiring structure, formed within the contact hole, prevents damage to the recessed plug during an etching process for forming the metal wiring structure. Therefore, the recessed plug may be formed without damage thereof even if an alignment error occurs between an etching mask and the recessed plug during metal wiring structure formation.

摘要翻译： 在基板上形成绝缘层之后，通过绝缘层形成接触孔。 形成一个凹形插头以部分地填充接触孔。 凹形插塞的高度显着小于接触孔的深度。 金属布线结构形成在凹形插塞和绝缘层上。 形成在接触孔内的金属布线结构的下部防止了在用于形成金属布线结构的蚀刻工艺期间对凹形插塞的损坏。 因此，即使在金属布线结构形成期间在蚀刻掩模和凹入插塞之间发生定向误差，也可以形成凹形插塞而不损坏凹形插塞。

公开(公告)号：US07253707B2

公开(公告)日：2007-08-07

申请号：US11141123

申请日：2005-05-31

申请人： Rajarshi Mukhopadhy ,  Sebastien Nuttinck ,  Sang-Hyun Woo ,  Jong-Han Kim ,  Seong-Soo Lee ,  Chang-Ho Lee ,  Joy Laskar

发明人： Rajarshi Mukhopadhy ,  Sebastien Nuttinck ,  Sang-Hyun Woo ,  Jong-Han Kim ,  Seong-Soo Lee ,  Chang-Ho Lee ,  Joy Laskar

IPC分类号： H03H11/00 ,  H03H11/04

CPC分类号： H03H11/50 ,  H03H11/48

摘要： An active inductor capable of tuning a self-resonant frequency, an inductance, a Q factor, and a peak Q frequency by applying a tunable feedback resistor to a cascode-grounded active inductor is disclosed. The tunable active inductor includes a first transistor having a source connected to a power supply voltage and a gate connected to first bias voltage; a second transistor having a drain connected to a drain of the first transistor and a gate connected to a second bias voltage; a third transistor having a drain connected to a source of the second transistor and a source connected to a ground voltage; a fourth transistor having a drain connected to a gate of the third transistor, a source connected to the ground voltage and a gate connected to a third bias voltage; a fifth transistor having a source connected to the drain of the fourth transistor and a drain connected to the power supply voltage.

摘要翻译： 公开了一种通过将可调谐反馈电阻器施加到共源共栅接地有源电感器来调谐自谐振频率，电感，Q因子和峰值Q频率的有源电感器。 可调谐有源电感器包括具有连接到电源电压的源极和连接到第一偏置电压的栅极的第一晶体管; 第二晶体管，具有连接到所述第一晶体管的漏极的漏极和连接到第二偏置电压的栅极; 具有连接到所述第二晶体管的源极的漏极和连接到接地电压的源极的第三晶体管; 具有连接到第三晶体管的栅极的漏极的第四晶体管，连接到接地电压的源极和连接到第三偏置电压的栅极; 第五晶体管，其源极连接到第四晶体管的漏极，漏极连接到电源电压。