公开(公告)号：US20130241042A1

公开(公告)日：2013-09-19

申请号：US13879911

申请日：2011-09-28

申请人： Yong-Tae Kwon

发明人： Yong-Tae Kwon

IPC分类号： H01L23/00

CPC分类号： H01L24/25 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/20 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/14511 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/1904 ,  H01L2924/19105

摘要： In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same.

摘要翻译： 在一个实施例中，半导体芯片封装包括具有形成在其中心的开口部分和围绕开口部分形成的通孔的绝缘框架; 半导体芯片，设置在所述开口部分上; 填充通孔的导电部分; 形成在半导体芯片的底面和绝缘框架上的内绝缘层，以露出导电部件的底面; 以及形成在所述内绝缘层上并且电连接所述半导体芯片和所述导电部件的内部信号图案。 实施例还涉及包括多个半导体芯片封装的垂直堆叠的半导体模块及其制造方法。

公开(公告)号：US06489182B2

公开(公告)日：2002-12-03

申请号：US09989494

申请日：2001-11-21

申请人： Yong-Tae Kwon

发明人： Yong-Tae Kwon

IPC分类号： H01L2148

CPC分类号： H01L24/10 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/4824 ,  H01L2224/48451 ,  H01L2224/48465 ,  H01L2224/48477 ,  H01L2224/4942 ,  H01L2224/73215 ,  H01L2224/85051 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/00

摘要： A chip size package is fabricated by: etching portions of a copper film on an insulating film tape, forming a solder mask on the insulating film tape excluding inner holes of metal pattern units and four edge portions of the copper film, electroplating, attaching the semiconductor chip, sealing the semiconductor chip with an epoxy, etching to expose the chip pads, electrically connecting the chip pads by wires, eliminating portions of the copper film remaining at the four edge portions and cutting the insulating film tape into individual units.

摘要翻译： 通过以下步骤制造芯片尺寸封装：通过在绝缘膜带上蚀刻铜膜的部分，在除了金属图案单元的内孔和铜膜的四个边缘部分之外的绝缘膜带上形成焊料掩模，电镀，将半导体 用环氧树脂密封半导体芯片，蚀刻以暴露芯片焊盘，通过电线电连接芯片焊盘，消除残留在四个边缘部分处的铜膜的部分并将绝缘膜带切割成单独的单元。

公开(公告)号：US09006872B2

公开(公告)日：2015-04-14

申请号：US13879911

申请日：2011-09-28

申请人： Yong-Tae Kwon

发明人： Yong-Tae Kwon

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/34 ,  H01L23/02 ,  H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L23/31

CPC分类号： H01L24/25 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/20 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/14511 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/1904 ,  H01L2924/19105

摘要： In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same.

摘要翻译： 在一个实施例中，半导体芯片封装包括具有形成在其中心的开口部分和围绕开口部分形成的通孔的绝缘框架; 半导体芯片，设置在所述开口部分上; 填充通孔的导电部分; 形成在半导体芯片的底面和绝缘框架上的内绝缘层，以露出导电部件的底面; 以及形成在所述内绝缘层上并且电连接所述半导体芯片和所述导电部件的内部信号图案。 实施例还涉及包括多个半导体芯片封装的垂直堆叠的半导体模块及其制造方法。

公开(公告)号：US20060032456A1

公开(公告)日：2006-02-16

申请号：US10533258

申请日：2003-10-01

申请人： Yong-Tae Kwon

发明人： Yong-Tae Kwon

IPC分类号： A01K1/03

CPC分类号： A01K1/0254

摘要： This invention is about a bag for a pet. It has fluid acceptation space which is suitable for physical character of a pet. Also it makes a pet safe and a man easy to walk as wearing more closer to his body. It consist of a main body which of space made bottom gradient to body direction from the front of be in pet's head, a form frame which set a pair with a flexible cushion on open surface and get smaller in diameter, and a changeable length shoulder strap which link both of a main body.

摘要翻译： 本发明涉及宠物袋。 它具有适合宠物身体特征的流体接受空间。 另外它使宠物安全，一个男人穿着更靠近他的身体，容易走路。 它包括一个主体，它的空间从宠物头部的前方向底部方向倾斜，形成框架，其在开放表面上设置一对柔性缓冲垫，并且具有更小的直径，以及可变长度的肩带 哪个链接两个主体。

公开(公告)号：US06339260B1

公开(公告)日：2002-01-15

申请号：US09394508

申请日：1999-09-13

申请人： Yong-Tae Kwon

发明人： Yong-Tae Kwon

IPC分类号： H01L2348

CPC分类号： H01L24/10 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/4824 ,  H01L2224/48451 ,  H01L2224/48465 ,  H01L2224/48477 ,  H01L2224/4942 ,  H01L2224/73215 ,  H01L2224/85051 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/00

摘要： A chip size package for a semiconductor device according to the present invention is fabricated by: etching a copper film applied on an insulating film tape, except for longitudinal marginal portions of the copper film, metal pattern units thereof which are peripheral to portions corresponding to chip pads of a semiconductor chip and portions thereof connecting the longitudinal marginal portions and the metal pattern units; forming a solder mask on the insulating film tape excluding inner holes of the metal pattern units, the copper film excluding four edge portions of the longitudinal marginal portions thereof and exterior circular marginal portions of the metal pattern units; electroplating portions of surfaces of the metal pattern units on which the solder mask is not formed, for thereby forming metal pattern unit-electroplates; attaching the semiconductor chip to a bottom surface of the insulating film tape; sealing side surfaces and a bottom surface of the semiconductor chip with an epoxy mold compound; etching portions of the insulating film tape formed on the chip pads for thereby exposing the chip pads; electrically connecting by wires the metal pattern unit-electrodes and the corresponding chip pads; and eliminating portions of the copper film remaining at the four edge portions of the longitudinal marginal portions thereof and cutting the resultant insulating film tape to be separated into individual units.

摘要翻译： 根据本发明的用于半导体器件的芯片尺寸封装通过以下方式制造：除了铜膜的纵向边缘部分之外，蚀刻施加在绝缘膜带上的铜膜，其对应于芯片的部分的周边的金属图案单元 半导体芯片的焊盘和连接纵向边缘部分和金属图案单元的部分; 在除了金属图案单元的内孔之外的绝缘膜带上形成除了其纵向边缘部分的四个边缘部分的铜膜和金属图案单元的外部圆形边缘部分之外的铜膜; 在其上未形成焊料掩模的金属图案单元的表面的电镀部分，从而形成金属图案单元电镀层; 将半导体芯片附接到绝缘膜带的底面; 用环氧树脂模塑料密封半导体芯片的侧表面和底表面; 蚀刻形成在芯片焊盘上的绝缘膜带的部分，从而使芯片焊盘露出; 通过电线电连接金属图案单元电极和相应的芯片焊盘; 并且除去残留在其纵向边缘部分的四个边缘部分处的铜膜的部分，并将所得到的绝缘膜带切割成单独的单元。