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    METHOD AND DRIVER FOR PROGRAMMING PHASE CHANGE MEMORY CELL
    4.
    发明申请
    METHOD AND DRIVER FOR PROGRAMMING PHASE CHANGE MEMORY CELL 失效
    编程相变记忆细胞的方法与驱动

    公开(公告)号：US20060181931A1

    公开(公告)日：2006-08-17

    申请号：US11401866

    申请日：2006-04-12

    申请人： Yong-ho Ha ,  Beak-hyung Cho ,  Ji-hye Yi

    发明人： Yong-ho Ha ,  Beak-hyung Cho ,  Ji-hye Yi

    IPC分类号： G11C16/06

    CPC分类号： G11C13/0069 ,  G11C7/04 ,  G11C13/0004 ,  G11C2013/0092

    摘要： In the method of programming a phase change memory cell, having a lower resistive state and a higher resistive state, to the lower resistive state, the memory cell is heated to first temperature. Subsequently, the memory cell is heated to second temperature, which is greater than the first temperature.

    摘要翻译： 在将具有较低电阻状态和较高电阻状态的相变存储单元编程为较低电阻状态的方法中，将存储单元加热至第一温度。 随后，将存储单元加热至大于第一温度的第二温度。

    Phase-change random access memory capable of reducing word line resistance
    7.
    发明授权
    Phase-change random access memory capable of reducing word line resistance 有权
    相位随机存取存储器能够减少字线电阻

    公开(公告)号：US08243495B2

    公开(公告)日：2012-08-14

    申请号：US12379399

    申请日：2009-02-20

    申请人： Byung-gil Choi ,  Won-ryul Chung ,  Beak-hyung Cho

    发明人： Byung-gil Choi ,  Won-ryul Chung ,  Beak-hyung Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C5/063 ,  G11C13/0004 ,  G11C2213/72

    摘要： A phase-change random access memory (PRAM) device capable of reducing a resistance of a word line may include a plurality of main word lines of a semiconductor memory device or PRAM bent n times in a layer different from a layer in which a plurality of sub-word lines are disposed. The semiconductor memory device or PRAM may further include jump contacts for connecting the plurality of cut sub-word lines. In a PRAM device including the plurality of main word lines and the plurality of sub-word lines being in different layers, the number of jump contacts for connecting the plurality of main word lines to a transistor of a sub-word line decoder is the same in each sub-word line or the plurality of main word lines are bent several times so that a parasitic resistance on a word line and power consumption may be reduced, and a sensing margin may be increased.

    摘要翻译： 能够降低字线的电阻的相变随机存取存储器（PRAM）装置可以包括半导体存储器件的多个主字线或在与多个 子字线被排列。 半导体存储器件或PRAM还可以包括用于连接多个切割子字线的跳跃触点。 在包括多个主字线和多个子字线在不同层中的PRAM装置中，用于将多个主字线连接到子字线解码器的晶体管的跳转触点的数量是相同的 在每个子字线或多个主字线被多次弯曲，从而可以减少字线上的寄生电阻和功耗，并且可以增加感测裕度。

    Phase change random access memory
    8.
    发明申请
    Phase change random access memory 有权

    公开(公告)号：US20090225590A1

    公开(公告)日：2009-09-10

    申请号：US12453420

    申请日：2009-05-11

    申请人： Hyung-rok Oh ,  Woo-Yeong Cho ,  Beak-hyung Cho

    发明人： Hyung-rok Oh ,  Woo-Yeong Cho ,  Beak-hyung Cho

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

    摘要： Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

    Nonvolatile memory device using variable resistive elements
    9.
    发明申请
    Nonvolatile memory device using variable resistive elements 有权
    使用可变电阻元件的非易失性存储器件

    公开(公告)号：US20080158941A1

    公开(公告)日：2008-07-03

    申请号：US12003442

    申请日：2007-12-26

    申请人： Byung-gil Choi ,  Beak-hyung Cho

    发明人： Byung-gil Choi ,  Beak-hyung Cho

    IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/18 ,  G11C13/0004 ,  G11C2029/2602 ,  H01L27/24

    摘要： The nonvolatile memory device includes a plurality of memory banks, each of which includes a plurality of nonvolatile memory cells. Each cell includes a variable resistive element having a resistance varying depending on stored data. A plurality of global bit lines are included, and each global bit line is shared by the plurality of memory banks. A plurality of main word lines are arranged corresponding to one of the plurality of memory banks.

    摘要翻译： 非易失性存储器件包括多个存储体，每个存储体包括多个非易失性存储单元。 每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件。 包括多个全局位线，并且每个全局位线被多个存储体共享。 多个主字线被布置成与多个存储体之一相对应。

    Phase-change semiconductor memory device and method of programming same
    10.
    发明授权
    Phase-change semiconductor memory device and method of programming same 有权
    相变半导体存储器件及其编程方法

    公开(公告)号：US07236393B2

    公开(公告)日：2007-06-26

    申请号：US11254853

    申请日：2005-10-21

    申请人： Beak-hyung Cho ,  Choong-keun Kwak

    发明人： Beak-hyung Cho ,  Choong-keun Kwak

    IPC分类号： G11C11/00

    CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/78 ,  G11C2213/79

    摘要： A semiconductor memory device and a method of programming the same, the semiconductor memory device includes a plurality of memory cells, each of the memory cells having a plurality of phase change variable resistors and a selection transistor. Each of the phase change variable resistors has a first end connected to one of a plurality of bit lines and a second end connected to a drain of the selection transistor. The selection transistor has a gate connected to a word line and a source connected to a reference voltage. The memory device is programmed by activating a word line associated with a selected memory cell, thereby turning on the selection transistor, applying a reset pulse to bit lines of the selected memory cell, and applying a set pulse to selected bit lines of the selected memory cell.

    摘要翻译： 半导体存储器件及其编程方法，半导体存储器件包括多个存储器单元，每个存储器单元具有多个相变可变电阻器和选择晶体管。 每个相变可变电阻器具有连接到多个位线之一的第一端和连接到选择晶体管的漏极的第二端。 选择晶体管具有连接到字线的栅极和连接到参考电压的源极。 通过激活与所选择的存储器单元相关联的字线来编程存储器件，从而导通选择晶体管，将复位脉冲施加到所选存储单元的位线，以及将设置的脉冲施加到所选存储器的选定位线 细胞。