公开(公告)号：US5497015A

公开(公告)日：1996-03-05

申请号：US435987

申请日：1989-11-13

申请人： Akira Ishibashi ,  Kenji Funato ,  Yoshifumi Mori

发明人： Akira Ishibashi ,  Kenji Funato ,  Yoshifumi Mori

IPC分类号： H01L29/66 ,  H01L29/775 ,  H01L29/80

CPC分类号： B82Y10/00 ,  H01L29/66977 ,  H01L29/775

摘要： A semiconductor device using interference effects of electron waves passing through a multichannel, wherein the multichannel is formed by a Dirac-delta-doped layer. A method of manufacturing a semiconductor device comprising the steps of: selectively forming a region of a predetermined crystallographic orientation onto a semiconductor substrate; and alternately growing the first semiconductor layer and the second semiconductor layer whose electron affinity is smaller than that of the first semiconductor layer onto the region of the predetermined crystallographic orientation by a vapor-phase growth method so as to have a convex shape in a manner such that an area of an upper layer is smaller. A semiconductor device in which a channel portion comprising a zigzag fine line is provided between a source and a drain.

摘要翻译： 使用通过多通道的电子波的干涉效应的半导体器件，其中多通道由狄拉克-δ掺杂层形成。 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上选择性地形成预定晶体取向的区域; 并且通过气相生长方法将电子亲和力小于第一半导体层的第一半导体层和第二半导体层交替地生长到具有预定结晶取向的区域上，从而具有凸形形状 上层的面积较小。 在源极和漏极之间设置有包括锯齿形细线的沟道部分的半导体器件。

公开(公告)号：US06438298B1

公开(公告)日：2002-08-20

申请号：US09616687

申请日：2000-07-14

申请人： Eriko Matsui ,  Akira Ishibashi ,  Yoshifumi Mori

发明人： Eriko Matsui ,  Akira Ishibashi ,  Yoshifumi Mori

IPC分类号： G02B626

CPC分类号： G02B6/2852 ,  G02B6/125

摘要： An optical device includes a plurality of first optical waveguides (or optical fibers) arranged in the horizontal direction; a plurality of second optical waveguides (or optical fibers) arranged on the same plane as the plane on which the first optical waveguides (or optical fibers) are arranged, the second optical waveguides (or optical fibers) being perpendicular or nearly perpendicular to the first optical waveguides (or optical fibers); and elements to be excited by light rays waveguided in the first and second optical waveguides(or optical fibers), the elements being arranged at crossing portions at which the first and second optical waveguides (or optical fibers) cross each other. In this display, the elements to be excited are selected for each line by intensities of light rays in the first optical waveguides (or optical fibers) functioning as horizontal waveguides (or optical fibers), and light rays in the second waveguides (or optical fibers) functioning as vertical waveguides (or optical fibers) are modulated in intensity on the basis of data signals, and the data signal light rays whose intensities have been modulated are extracted to the outside via the selected elements to be excited.

摘要翻译： 光学装置包括沿水平方向布置的多个第一光波导（或光纤）; 布置在与其上布置有第一光波导（或光纤）的平面相同的平面上的多个第二光波导（或光纤），第二光波导（或光纤）垂直于或几乎垂直于第一光波导 光波导（或光纤）; 以及要在第一和第二光波导（或光纤）中波导的光线激发的元件，元件布置在第一和第二光波导（或光纤）彼此交叉的交叉部分。 在该显示中，通过用作水平波导（或光纤）的第一光波导（或光纤）中的光线的强度，针对每一行选择要激发的元件，并且第二波导（或光纤）中的光线 ）作为垂直波导（或光纤）的功能在数据信号的基础上进行强度调制，并且已经调制了强度的数据信号光线经由被激励的选定元件提取到外部。

公开(公告)号：US5247223A

公开(公告)日：1993-09-21

申请号：US723974

申请日：1991-07-01

申请人： Yoshifumi Mori ,  Akira Ishibashi

发明人： Yoshifumi Mori ,  Akira Ishibashi

IPC分类号： H01J9/02 ,  H01J21/10 ,  H01J1/30

CPC分类号： H01J21/105 ,  H01J9/025

摘要： A quantum interference semiconductor device using the interference effect of electron waves has a cathode, an anode, and a gate which are mounted in a vacuum. An electron wave which is emitted from the cathode into the vacuum is divided into a plurality of electron waves and, subsequently, the plurality of electron waves are combined at the anode. Phase differences among the plurality of electron waves are controlled by the gate, thereby making the device operative.

摘要翻译： 使用电子束的干涉效应的量子干涉半导体器件具有安装在真空中的阴极，阳极和栅极。 从阴极发射到真空中的电子波被分成多个电子波，随后在阳极处组合多个电子波。 多个电子波之间的相位差由栅极控制，从而使器件工作。

公开(公告)号：US4937204A

公开(公告)日：1990-06-26

申请号：US293333

申请日：1989-01-04

申请人： Akira Ishibashi ,  Yoshifumi Mori ,  Masao Itabashi

发明人： Akira Ishibashi ,  Yoshifumi Mori ,  Masao Itabashi

IPC分类号： H01L29/80 ,  H01L21/205 ,  H01L29/15 ,  H01L29/68 ,  H01L29/737

CPC分类号： H01L29/155 ,  H01L29/7376 ,  Y10S148/011 ,  Y10S148/056 ,  Y10S148/072 ,  Y10S148/097 ,  Y10S148/119 ,  Y10S148/16

摘要： A semiconductor apparatus is disclosed, in which the entire or part of an electron active region is formed by a superlattice structure semiconductor layer in which a plurality of different semiconductor layers, less than 8 monolayers, and containing a fraction or a binary compound semiconductor layers are alternately and epitaxially grown and a main current direction is selected to be in the direction perpendicular to the laminae of said superlattice layers.

公开(公告)号：US5732099A

公开(公告)日：1998-03-24

申请号：US686473

申请日：1996-07-25

申请人： Takayuki Kawasumi ,  Norikazu Nakayama ,  Akira Ishibashi ,  Yoshifumi Mori

发明人： Takayuki Kawasumi ,  Norikazu Nakayama ,  Akira Ishibashi ,  Yoshifumi Mori

IPC分类号： H01S5/00 ,  H01S5/223 ,  H01S5/327 ,  H01S5/347 ,  H01S3/19 ,  H01L33/00

CPC分类号： H01L33/24 ,  B82Y20/00 ,  H01L33/28 ,  H01S5/2232 ,  H01S5/347 ,  H01S5/2235 ,  H01S5/2237 ,  H01S5/327

摘要： A p-type GaAs current block layer is stacked on a (100)-oriented n-type GaAs substrate, and a stripe-shaped groove is formed in the p-type GaAs current block layer to extend in the direction. Side surfaces of the groove has the maximum inclination not larger than 60.degree.. The thickness of the p-type GaAs current block layer is 1.5 .mu.m or more. Stacked on the structured substrate having the current narrowed mechanism via an n-type ZnSe buffer layer are an n-type ZnMgSSe cladding layer, n-type ZnSSe waveguide layer, active layer, p-type ZnSSe waveguide layer, p-type ZnMgSSe cladding layer, and others, to establish an index-guided inner-striped semiconductor laser having SCH structure and CSPW structure.

摘要翻译： 在（100）取向的n型GaAs衬底上堆叠p型GaAs电流阻挡层，并且在p型GaAs电流阻挡层中形成条形槽，以沿<01-1>方向延伸 。 槽的侧面最大倾角不大于60°。 p型GaAs电流阻挡层的厚度为1.5μm以上。 通过n型ZnSe缓冲层堆叠在具有电流变窄机构的结构化衬底上是n型ZnMgSSe包层，n型ZnSSe波导层，有源层，p型ZnSSe波导层，p型ZnMgSSe覆层 等，建立了具有SCH结构和CSPW结构的折射率引导内条纹半导体激光器。

公开(公告)号：US5147823A

公开(公告)日：1992-09-15

申请号：US707236

申请日：1991-05-22

申请人： Akira Ishibashi ,  Yoshifumi Mori ,  Kenji Funato

发明人： Akira Ishibashi ,  Yoshifumi Mori ,  Kenji Funato

IPC分类号： G03F7/004 ,  G03F7/20

CPC分类号： G03F7/2041 ,  G03F7/004 ,  Y10S148/046 ,  Y10S438/949

摘要： In a method for forming a pattern, by selectively irradiating a charged particle beam onto a substrate in an atmosphere containing a raw material gas, a resist pattern comprising a material which is produced on the substrate from the raw material gas is formed, wherein a pressure of the raw material gas is set to 10.sup.-7 to 10.sup.-5 Torr, an accelerating voltage of the charged particle beam is set to 0.5 to 6 kV, and a beam current of the charged particle beam is set to 10.sup.-13 to 10.sup.-7 A. Thus, a resist pattern of an ultrafine width can be stably formed in a relatively short time.Further, in a method for forming a pattern, by irradiating a charged particle beam onto a substrate in an atmosphere containing a gaseous negative type resist, a cross-linking reaction of the negative type resist molecules adsorbed on the surface of the substrate is caused, and a pattern comprising the negative type resist molecules which caused the cross-linking reaction is formed, so that a pattern which has an ultrafine width and can be easily removed by the wet process can be formed.

公开(公告)号：US5171718A

公开(公告)日：1992-12-15

申请号：US639325

申请日：1991-01-09

申请人： Akira Ishibashi ,  Yoshifumi Mori ,  Kenji Funato

发明人： Akira Ishibashi ,  Yoshifumi Mori ,  Kenji Funato

IPC分类号： G03F7/004 ,  G03F7/20

CPC分类号： G03F7/004 ,  G03F7/2041 ,  Y10S148/10 ,  Y10S148/131 ,  Y10S148/137 ,  Y10S438/949

摘要： A fine pattern formation using an electron beam induced resist, and use of the resist in making semiconductor devices are disclosed. Collimated electron beam is irradiated and scanned along a desired pattern on a layer on which a resist layer of a desired pattern is deposited under an atmosphere containing a starting material layer for the resist. The resist thus deposited is partially removed by reactive ion etching to remove the skirt like portion of the resist layer, or totally removed by reactive ion etching during or after processing by using the resist layer as a processing mask. Since the resist layer width is determined by a diameter of the collimated electron beam, line width of less than hundred .ANG. can be directly drawn. There are also disclosed processes using the resist layer in manufacturing semiconductor devices.

摘要翻译： 公开了使用电子束感应抗蚀剂的精细图案形成，以及在制造半导体器件中使用抗蚀剂。 沿着期望的图案沿着期望的图案照射准直的电子束，在其上沉积有所需图案的抗蚀剂层的层上，在含有抗蚀剂的起始材料层的气氛下。 通过反应离子蚀刻部分去除由此沉积的抗蚀剂以去除抗蚀剂层的裙状部分，或者通过使用抗蚀剂层作为处理掩模在处理期间或之后通过反应离子蚀刻完全除去。 由于抗蚀剂层宽度由准直电子束的直径确定，所以可以直接绘制小于100的棱线宽度。 还公开了在制造半导体器件中使用抗蚀剂层的工艺。

公开(公告)号：US5156988A

公开(公告)日：1992-10-20

申请号：US757605

申请日：1991-09-11

申请人： Yoshifumi Mori ,  Akira Ishibashi

发明人： Yoshifumi Mori ,  Akira Ishibashi

IPC分类号： H01J9/02 ,  H01J21/10

CPC分类号： H01J21/105 ,  H01J9/025 ,  Y10S438/962

摘要： A method of making a quantum interference semiconductor device comprising the steps of forming a first semiconductor layer on a semi-insulating semiconductor substrate, forming a semi-insulating second semiconductor layer on the first semiconductor layer, forming a metal film so as to form a gate electrode on the second semiconductor layer, forming a first opening by selectively removing the metal film to form the gate electrode, forming a mask on the first opening and etching until midway in the film thickness direction of the semi-insulative second semiconductor layer by anitropic etching through said first opening and subsequently forming an etching until an upper surface of the semiconductor substrate by isotropic etching occurs so as to form a second opening into the semi-insulative second semiconductor layer and the first semiconductor layer which is continuous with the first opening portion and forming a cathode from the first semiconductor layer and a blocker made of the second semiconductor layer.

摘要翻译： 一种制造量子干涉半导体器件的方法，包括以下步骤：在半绝缘半导体衬底上形成第一半导体层，在第一半导体层上形成半绝缘的第二半导体层，形成金属膜以形成栅极 在第二半导体层上形成第一开口，通过选择性地去除金属膜以形成栅电极，在第一开口上形成掩模，并通过无孔蚀刻蚀刻直到半绝缘性第二半导体层的膜厚度方向的中间 通过所述第一开口并随后形成蚀刻，直到半导体衬底的上表面通过各向同性蚀刻发生，以形成到半绝缘性第二半导体层和与第一开口部分连续的第一半导体层的第二开口，以及 从第一半导体层形成阴极和由第二半导体层制成的阻挡层 半导体层。

公开(公告)号：US4888622A

公开(公告)日：1989-12-19

申请号：US271911

申请日：1988-11-16

申请人： Akira Ishibashi ,  Kenji Funato ,  Yoshifumi Mori

发明人： Akira Ishibashi ,  Kenji Funato ,  Yoshifumi Mori

IPC分类号： H01L39/22 ,  H03K17/92

CPC分类号： H01L39/228

摘要： A superconducting electron device is disclosed, in which a pair of parallel superconducting channels each having a Josephson junction therein are provided between source and drain electrodes, and a gate electrode is provided to apply a voltage to the channels to make potentials at each channels different to each other. The current flow through channels is controlled by the application of a voltage to the gate electrode based on electrostatic Aharanov-Bohm effect. The device uses the coherency characteristics of the superconducting material, thus high speed switching operation can be achieved.

摘要翻译： 公开了一种超导电子器件，其中在源电极和漏电极之间设置一对均具有约瑟夫逊结的平行超导通道，并且提供栅电极以向通道施加电压，以使各通道的电位不同于 彼此。 通过通道的电流通过基于静电Aharanov-Bohm效应向栅电极施加电压来控制。 该器件采用超导材料的相干特性，可实现高速切换操作。

公开(公告)号：US4835579A

公开(公告)日：1989-05-30

申请号：US839712

申请日：1986-03-13

申请人： Akira Ishibashi ,  Yoshifumi Mori ,  Masao Itabashi

发明人： Akira Ishibashi ,  Yoshifumi Mori ,  Masao Itabashi

IPC分类号： H01L29/80 ,  H01L21/205 ,  H01L29/15 ,  H01L29/68 ,  H01L29/737

CPC分类号： H01L29/155 ,  H01L29/7376 ,  Y10S148/011 ,  Y10S148/056 ,  Y10S148/072 ,  Y10S148/097 ,  Y10S148/119 ,  Y10S148/16

摘要： A semiconductor apparatus is disclosed, in which the entire or part of an electron active region is formed by a superlattice structure semiconductor layer in which a plurality of different semiconductor layers, less than 8 monolayers, and containing a fraction or a binary compound semiconductor layers are alternately and epitaxially grown and a main current direction is selected to be in the direction perpendicular to the laminae of said superlattice layers.

摘要翻译： 公开了一种半导体装置，其中电子有源区的全部或一部分由超晶格结构半导体层形成，其中多个不同的半导体层（小于8个单层）并且包含一部分或二元化合物半导体层是 交替地并外延生长，并且主电流方向被选择为在垂直于所述超晶格层的层的方向上。