公开(公告)号：US20070045639A1

公开(公告)日：2007-03-01

申请号：US11508921

申请日：2006-08-24

申请人： Sadahiro Kato ,  Yoshihiro Sato ,  Seikoh Yoshida

发明人： Sadahiro Kato ,  Yoshihiro Sato ,  Seikoh Yoshida

IPC分类号： H01L33/00

CPC分类号： H01L29/7787 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205

摘要： A semiconductor electronic device includes a buffer layer formed on a substrate, and a semiconductor operating layer that is formed on the buffer layer. The semiconductor operating layer includes a nitride-based compound semiconductor and. The buffer layer includes at least one composite layer that includes a first layer and a second layer. A lattice-constant difference between the first layer and the second layer is equal to or more than 0.2 percent.

摘要翻译： 半导体电子器件包括形成在衬底上的缓冲层和形成在缓冲层上的半导体操作层。 半导体工作层包括氮化物基化合物半导体。 缓冲层包括至少一个包括第一层和第二层的复合层。 第一层和第二层之间的晶格常数差等于或大于0.2％。

公开(公告)号：US20090278172A1

公开(公告)日：2009-11-12

申请号：US12382010

申请日：2009-03-05

申请人： Shusuke Kaya ,  Seikoh Yoshida ,  Sadahiro Kato ,  Takehiko Nomura ,  Nariaki Ikeda ,  Masayuki Iwami ,  Yoshihiro Sato ,  Hiroshi Kambayashi ,  Yuki Niiyama ,  Masatoshi Ikeda

发明人： Shusuke Kaya ,  Seikoh Yoshida ,  Sadahiro Kato ,  Takehiko Nomura ,  Nariaki Ikeda ,  Masayuki Iwami ,  Yoshihiro Sato ,  Hiroshi Kambayashi ,  Yuki Niiyama ,  Masatoshi Ikeda

IPC分类号： H01L29/205

CPC分类号： H01L29/0847 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7787

摘要： The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.

摘要翻译： 场效应晶体管包括其中缓冲层和电子传输层（未掺杂的GaN层）和电子供应层（未掺杂的AlGaN层）依次叠置在蓝宝石衬底上的叠层结构。 在电子供给层的源极区域上形成npn层叠结构，在npn层叠结构上形成源电极。 在电子供给层的漏极区域中形成漏电极，并且在形成在栅极区域的开口区域中形成绝缘膜。 当向栅电极施加大于阈值的正向电压时，形成反型层，漏极电流流动。 通过改变p型GaN层的厚度和杂质浓度，可以控制阈值电压。 由于漂移层，栅极电极和漏电极之间的电场浓度被松弛，并且耐电压提高。

公开(公告)号：US20090140295A1

公开(公告)日：2009-06-04

申请号：US12292164

申请日：2008-11-13

申请人： Shusuke Kaya ,  Seikoh Yoshida ,  Sadahiro Kato ,  Takehiko Nomura ,  Nariaki Ikeda ,  Masayuki Iwami ,  Yoshihiro Sato ,  Hiroshi Kambayashi ,  Koh Li

发明人： Shusuke Kaya ,  Seikoh Yoshida ,  Sadahiro Kato ,  Takehiko Nomura ,  Nariaki Ikeda ,  Masayuki Iwami ,  Yoshihiro Sato ,  Hiroshi Kambayashi ,  Koh Li

IPC分类号： H01L29/737 ,  H01L21/28 ,  H01L21/265

CPC分类号： H01L29/7787 ,  H01L29/0611 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/66462

摘要： A GaN-based semiconductor device includes a silicon substrate; an active layer of a GaN-based semiconductor formed on the silicon substrate; a trench formed in the active layer and extending from a top surface of the active layer to the silicon substrate; a first electrode formed on an internal wall surface of the trench so that the first electrode extends from the top surface of the active layer to the silicon substrate; a second electrode formed on the active layer so that a current flows between the first electrode and the second electrode via the active layer; and a bottom electrode formed on a bottom surface of the silicon substrate. The first electrode is formed of a metal capable of being in ohmic contact with the silicon substrate and the active layer.

摘要翻译： GaN基半导体器件包括硅衬底; 形成在硅衬底上的GaN基半导体的有源层; 形成在有源层中并从有源层的顶表面延伸到硅衬底的沟槽; 形成在所述沟槽的内壁表面上的第一电极，使得所述第一电极从所述有源层的顶表面延伸到所述硅衬底; 形成在有源层上的第二电极，使得电流经由有源层在第一电极和第二电极之间流动; 以及形成在硅衬底的底表面上的底部电极。 第一电极由能够与硅衬底和有源层欧姆接触的金属形成。

公开(公告)号：US08304809B2

公开(公告)日：2012-11-06

申请号：US12292164

申请日：2008-11-13

申请人： Shusuke Kaya ,  Seikoh Yoshida ,  Masatoshi Ikeda, legal representative ,  Sadahiro Kato ,  Takehiko Nomura ,  Nariaki Ikeda ,  Masayuki Iwami ,  Yoshihiro Sato ,  Hiroshi Kambayashi ,  Koh Li

发明人： Shusuke Kaya ,  Seikoh Yoshida ,  Sadahiro Kato ,  Takehiko Nomura ,  Nariaki Ikeda ,  Masayuki Iwami ,  Yoshihiro Sato ,  Hiroshi Kambayashi ,  Koh Li

IPC分类号： H01L29/737 ,  H01L21/28 ,  H01L21/265

CPC分类号： H01L29/7787 ,  H01L29/0611 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/66462

摘要： In a GaN-based semiconductor device, an active layer of a GaN-based semiconductor is formed on a silicon substrate. A trench is formed in the active layer and extends from a top surface of the active layer to a depth reaching the silicon substrate. A first electrode is formed on an internal wall surface of the trench and extends from the top surface of the active layer to the silicon substrate. A second electrode is formed on the active layer to define a current path between the first electrode and the second electrode via the active layer in an on-state of the device. A bottom electrode is formed on a bottom surface of the silicon substrate and defines a bonding pad for the first electrode. The first electrode is formed of metal in direct ohmic contact with both the silicon substrate and the active layer.

摘要翻译： 在GaN基半导体器件中，在硅衬底上形成GaN基半导体的有源层。 在有源层中形成沟槽并从有源层的顶表面延伸到达到硅衬底的深度。 第一电极形成在沟槽的内壁表面上并从有源层的顶表面延伸到硅衬底。 第二电极形成在有源层上，以在器件的导通状态中经由有源层在第一电极和第二电极之间限定电流路径。 底部电极形成在硅衬底的底表面上，并且限定了用于第一电极的焊盘。 第一电极由与硅衬底和有源层直接欧姆接触的金属形成。

公开(公告)号：US08134181B2

公开(公告)日：2012-03-13

申请号：US12539736

申请日：2009-08-12

申请人： Yoshihiro Sato ,  Sadahiro Kato ,  Seikoh Yoshida

发明人： Yoshihiro Sato ,  Sadahiro Kato ,  Seikoh Yoshida

IPC分类号： H01L29/778

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

摘要： A semiconductor device includes a substrate; a buffer layer; and a compound semiconductor layer laminated on the substrate with the buffer layer in between. The buffer layer has a dislocation density in a plane in parallel to an in-plane direction thereof, so that a volume resistivity of the buffer layer becomes a substantially maximum value.

摘要翻译： 半导体器件包括衬底; 缓冲层; 以及层叠在基板上的化合物半导体层之间的缓冲层。 缓冲层在与其面内方向平行的平面中具有位错密度，使得缓冲层的体积电阻率变为基本上最大值。

公开(公告)号：US07812371B2

公开(公告)日：2010-10-12

申请号：US12382010

申请日：2009-03-05

申请人： Shusuke Kaya ,  Seikoh Yoshida ,  Masatoshi Ikeda, legal representative ,  Sadahiro Kato ,  Takehiko Nomura ,  Nariaki Ikeda ,  Masayuki Iwami ,  Yoshihiro Sato ,  Hiroshi Kambayashi ,  Yuki Niiyama

发明人： Shusuke Kaya ,  Seikoh Yoshida ,  Sadahiro Kato ,  Takehiko Nomura ,  Nariaki Ikeda ,  Masayuki Iwami ,  Yoshihiro Sato ,  Hiroshi Kambayashi ,  Yuki Niiyama

IPC分类号： H01L31/072

CPC分类号： H01L29/0847 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7787

摘要： The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.

摘要翻译： 场效应晶体管包括其中缓冲层和电子传输层（未掺杂的GaN层）和电子供体层（未掺杂的AlGaN层）依次层叠在蓝宝石衬底上的叠层结构。 在电子供给层的源极区域上形成npn层叠结构，在npn层叠结构上形成源电极。 在电子供给层的漏极区域中形成漏电极，并且在形成在栅极区域的开口区域中形成绝缘膜。 当向栅电极施加大于阈值的正向电压时，形成反型层，漏极电流流动。 通过改变p型GaN层的厚度和杂质浓度，可以控制阈值电压。 由于漂移层，栅极电极和漏电极之间的电场浓度被松弛，并且耐电压提高。

公开(公告)号：US20100032716A1

公开(公告)日：2010-02-11

申请号：US12539736

申请日：2009-08-12

申请人： Yoshihiro Sato ,  Sadahiro Kato ,  Seikoh Yoshida

发明人： Yoshihiro Sato ,  Sadahiro Kato ,  Seikoh Yoshida

IPC分类号： H01L29/772 ,  H01L29/861

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

摘要： A semiconductor device includes a substrate; a buffer layer; and a compound semiconductor layer laminated on the substrate with the buffer layer in between. The buffer layer has a dislocation density in a plane in parallel to an in-plane direction thereof, so that a volume resistivity of the buffer layer becomes a substantially maximum value.

摘要翻译： 半导体器件包括衬底; 缓冲层; 以及层叠在基板上的化合物半导体层之间的缓冲层。 缓冲层在与其面内方向平行的平面中具有位错密度，使得缓冲层的体积电阻率变为基本上最大值。

公开(公告)号：US08421182B2

公开(公告)日：2013-04-16

申请号：US12639199

申请日：2009-12-16

申请人： Takehiko Nomura ,  Seikoh Yoshida ,  Sadahiro Kato

发明人： Takehiko Nomura ,  Seikoh Yoshida ,  Sadahiro Kato

IPC分类号： H01L31/062

CPC分类号： H01L29/063 ,  H01L29/2003

摘要： A semiconductor layer of a second conductive type is formed on a RESURF layer of a first conductive type that is formed on a buffer layer. A contact layer of the first conductive type is formed in or on the semiconductor layer. A source electrode is formed on the contact layer. A drain electrode is formed on the RESURF layer. A gate insulating film is formed on the semiconductor layer to overlap with an end of the semiconductor layer. A gate electrode is formed on the gate insulating film to overlap with the end of the semiconductor layer. A channel formed near the end of the semiconductor layer is electrically connected to the RESURF layer.

摘要翻译： 在形成在缓冲层上的第一导电类型的RESURF层上形成第二导电类型的半导体层。 第一导电类型的接触层形成在半导体层中或半导体层上。 源电极形成在接触层上。 在RESURF层上形成漏电极。 在半导体层上形成栅极绝缘膜，与半导体层的端部重叠。 栅电极形成在栅极绝缘膜上以与半导体层的端部重叠。 在半导体层的端部附近形成的沟道电连接到RESURF层。

公开(公告)号：US20100127307A1

公开(公告)日：2010-05-27

申请号：US12639199

申请日：2009-12-16

申请人： Takehiko Nomura ,  Seikoh Yoshida ,  Sadahiro Kato

发明人： Takehiko Nomura ,  Seikoh Yoshida ,  Sadahiro Kato

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/063 ,  H01L29/2003

摘要： A semiconductor layer of a second conductive type is formed on a RESURF layer of a first conductive type that is formed on a buffer layer. A contact layer of the first conductive type is formed in or on the semiconductor layer. A source electrode is formed on the contact layer. A drain electrode is formed on the RESURF layer. A gate insulating film is formed on the semiconductor layer to overlap with an end of the semiconductor layer. A gate electrode is formed on the gate insulating film to overlap with the end of the semiconductor layer. A channel formed near the end of the semiconductor layer is electrically connected to the RESURF layer.

摘要翻译： 在形成在缓冲层上的第一导电类型的RESURF层上形成第二导电类型的半导体层。 第一导电类型的接触层形成在半导体层中或半导体层上。 源电极形成在接触层上。 在RESURF层上形成漏电极。 在半导体层上形成栅极绝缘膜，与半导体层的端部重叠。 栅电极形成在栅极绝缘膜上以与半导体层的端部重叠。 在半导体层的端部附近形成的沟道电连接到RESURF层。

公开(公告)号：US08450782B2

公开(公告)日：2013-05-28

申请号：US13075843

申请日：2011-03-30

申请人： Yoshihiro Sato ,  Takehiko Nomura ,  Nariaki Ikeda ,  Takuya Kokawa ,  Masayuki Iwami ,  Sadahiro Kato

发明人： Yoshihiro Sato ,  Takehiko Nomura ,  Nariaki Ikeda ,  Takuya Kokawa ,  Masayuki Iwami ,  Sadahiro Kato

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787

摘要： A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm−3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.

摘要翻译： 场效应晶体管包括在基板上的高电阻层，形成在高电阻层上并具有碳浓度不大于1×10 18 cm -3且具有层厚度的沟道层的半导体操作层 大于10nm且不大于100nm的凹槽，形成在半导体操作层中的沟道层内部的凹部，形成在半导体操作层上的沟槽间的沟槽间的沟槽间的沟槽， 栅极绝缘膜，其形成在半导体操作层上以覆盖凹部;以及栅电极，其形成在凹部中的栅极绝缘膜上。