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    Semiconductor device and manufacturing method of semiconductor device
    6.
    发明授权
    Semiconductor device and manufacturing method of semiconductor device 有权
    半导体器件及半导体器件的制造方法

    公开(公告)号：US08865589B2

    公开(公告)日：2014-10-21

    申请号：US13614217

    申请日：2012-09-13

    申请人： Takaki Hashimoto ,  Yasunobu Kai ,  Toshiya Kotani

    发明人： Takaki Hashimoto ,  Yasunobu Kai ,  Toshiya Kotani

    IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/033 ,  H01L27/115

    CPC分类号： H01L23/528 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76895 ,  H01L27/11519 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

    摘要： According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality at first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires.

    摘要翻译： 根据一个实施例，半导体器件包括以预定间距平行布置的多条导线，多个第一触点分别连接到导线之间的奇数编号，并且与正交方向平行布置，与 与导线的布线方向相连接的多个第二触点，以及多个第二触点，每个第二触点各自连接到电线中的偶数线，并且相对于线的布线方向在正交方向上平行布置， 在与导线的布线方向正交的方向上的第一触点相对于第二触点偏离线的间距的方式偏离布线方向的第一触点。

    Semiconductor device manufacturing method
    7.
    发明授权
    Semiconductor device manufacturing method 有权
    半导体器件制造方法

    公开(公告)号：US08293456B2

    公开(公告)日：2012-10-23

    申请号：US12390157

    申请日：2009-02-20

    申请人： Kazuya Fukuhara ,  Takaki Hashimoto ,  Kazuyuki Masukawa ,  Yasunobu Kai

    发明人： Kazuya Fukuhara ,  Takaki Hashimoto ,  Kazuyuki Masukawa ,  Yasunobu Kai

    IPC分类号： G03F1/00

    CPC分类号： G03F1/00 ,  G03F1/36 ,  G03F7/70433

    摘要： A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude.

    摘要翻译： 一种半导体器件制造方法，包括将照明光施加到光掩模，以及经由投影光学系统从光掩模投射衍射光成分，以在基板上形成光刻胶图案。 光掩模包括多个开口图案，其以在第二方向上的规则的第二间隔布置在多条平行线中的每一条上，并且在垂直于第二方向的第一方向上具有规则的第一间隔。 布置在多条平行线上相邻的多个平行线上的多个开口图案在第二方向上相互偏移第二间隔的一半。 此外，设置多个开口图案的尺寸和光掩模中的非透明区域的复振幅透射率，使得穿过投影光学系统的光瞳的三个衍射光分量具有相等的幅度。

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：US20100202181A1

    公开(公告)日：2010-08-12

    申请号：US12561531

    申请日：2009-09-17

    申请人： Takaki HASHIMOTO ,  Hidefumi Mukai ,  Yasunobu Kai ,  Toshiya Kotani

    发明人： Takaki HASHIMOTO ,  Hidefumi Mukai ,  Yasunobu Kai ,  Toshiya Kotani

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C5/025

    摘要： A semiconductor memory device includes a semiconductor substrate on which memory cells are formed. Interconnects are arranged along a first direction above the semiconductor substrate, and have regular intervals along a second direction perpendicular to the first direction. Interconnect contacts connect the interconnects and the semiconductor substrate, are arranged on three or more rows. The center of each of two of the interconnect contacts which are connected to the interconnects adjacent in the second direction deviate from each other along the first direction.

    摘要翻译： 半导体存储器件包括形成有存储单元的半导体衬底。 互连件沿着半导体衬底上方的第一方向布置，并且沿着垂直于第一方向的第二方向具有规则的间隔。 互连触点连接互连和半导体衬底，布置在三行或更多行上。 连接到在第二方向相邻的互连件的两个互连触点中的每一个的中心沿着第一方向彼此偏离。

    Photomask designing method and photomask designing program
    9.
    发明授权
    Photomask designing method and photomask designing program 有权
    光掩模设计方法和光掩模设计程序

    公开(公告)号：US08423922B2

    公开(公告)日：2013-04-16

    申请号：US12850082

    申请日：2010-08-04

    申请人： Yasunobu Kai

    发明人： Yasunobu Kai

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G03F1/36

    摘要： In one embodiment, a photomask designing method for creating a pattern layout having an assist pattern placed around a design pattern is disclosed. The method can place a plurality of evaluation points around the design pattern and set an evaluation index for imaging properties of the design pattern on an imaging surface. The method can combine a light intensity distribution of the design pattern with light intensity distributions of the evaluation points to obtain a light intensity distribution on the imaging surface and evaluate the light intensity distribution on the imaging surface using the evaluation index to determine a region having an effective evaluation point placed. In addition, the method can determine a placement condition for the assist pattern based on the region where the effective evaluation point is placed and place the assist pattern around the design pattern based on the placement condition to create the pattern layout.

    摘要翻译： 在一个实施例中，公开了一种用于创建具有围绕设计图案放置的辅助图案的图案布局的光掩模设计方法。 该方法可以围绕设计图案放置多个评估点，并且在成像表面上设置用于设计图案的成像属性的评估指标。 该方法可以将设计图案的光强度分布与评估点的光强度分布组合以获得成像表面上的光强度分布，并使用评估指数评估成像表面上的光强度分布，以确定具有 有效的评估点放置。 此外，该方法可以基于放置有效评估点的区域来确定辅助图案的放置条件，并且基于放置条件将辅助图案围绕设计图案放置以创建图案布局。

    SEMICONDUCTOR DEVICE MANUFACTURING METHOD
    10.
    发明申请
    SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
    半导体器件制造方法

    公开(公告)号：US20120328992A1

    公开(公告)日：2012-12-27

    申请号：US13606834

    申请日：2012-09-07

    申请人： Kazuya Fukuhara ,  Takaki Hashimoto ,  Kazuyuki Masukawa ,  Yasunobu Kai

    发明人： Kazuya Fukuhara ,  Takaki Hashimoto ,  Kazuyuki Masukawa ,  Yasunobu Kai

    IPC分类号： G03F7/20

    CPC分类号： G03F1/00 ,  G03F1/36 ,  G03F7/70433

    摘要： A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude.

    摘要翻译： 一种半导体器件制造方法，包括将照明光施加到光掩模，以及经由投影光学系统从光掩模投射衍射光成分，以在基板上形成光刻胶图案。 光掩模包括多个开口图案，其以在第二方向上的规则的第二间隔布置在多条平行线中的每一条上，并且在垂直于第二方向的第一方向上具有规则的第一间隔。 布置在多条平行线上相邻的多个平行线上的多个开口图案在第二方向上相互偏移第二间隔的一半。 此外，设置多个开口图案的尺寸和光掩模中的非透明区域的复振幅透射率，使得穿过投影光学系统的光瞳的三个衍射光分量具有相等的幅度。