公开(公告)号：US06777775B2

公开(公告)日：2004-08-17

申请号：US10187378

申请日：2002-07-02

申请人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

发明人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

IPC分类号： H01L2900

CPC分类号： H01L27/0805 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

摘要翻译： 半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。 这些电极分别连接到上电极布线和下电极。 当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在 上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。 因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

公开(公告)号：US07777293B2

公开(公告)日：2010-08-17

申请号：US10898965

申请日：2004-07-27

申请人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

发明人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

IPC分类号： H01L29/93

CPC分类号： H01L27/0805 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

摘要翻译： 半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。 这些电极分别连接到上电极布线和下电极。 当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在 上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。 因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

公开(公告)号：US06927723B2

公开(公告)日：2005-08-09

申请号：US10855397

申请日：2004-05-28

申请人： Daisuke Nomasaki ,  Kenji Murata ,  Hideki Tanaka ,  Yoshinori Miyada

发明人： Daisuke Nomasaki ,  Kenji Murata ,  Hideki Tanaka ,  Yoshinori Miyada

IPC分类号： H03M1/12 ,  H03M1/46

CPC分类号： H03M1/124 ,  H03M1/468

摘要： In a charge redistribution type A/D converter, an input-side capacitor terminal and a comparator-side capacitor terminal are connected through first and second analog switches to a fixed-voltage supply circuit, and the input-side capacitor terminal is connected through a third analog switch to the outside. Immediately before sampling an analog signal, the first and second analog switches are closed while the third analog switch is opened, according to a RESET signal. Thereby, fixed voltages are supplied to the input-side capacitor terminal and the comparator-side capacitor terminal, respectively, and charge stored in a weighting capacitor unit is initialized to a predetermined value.

摘要翻译： 在电荷再分配型A / D转换器中，输入侧电容器端子和比较器侧电容器端子通过第一和第二模拟开关连接到固定电压电源电路，并且输入侧电容器端子通过 第三个模拟开关到外面。 在采样模拟信号之前，根据RESET信号，第三模拟开关打开时，第一和第二模拟开关闭合。 由此，固定电压分别被提供给输入侧电容器端子和比较器侧电容器端子，并将存储在加权电容器单元中的电荷初始化为预定值。

公开(公告)号：US20050001291A1

公开(公告)日：2005-01-06

申请号：US10898965

申请日：2004-07-27

申请人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

发明人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/522 ,  H01L27/08 ,  H01L23/552

CPC分类号： H01L27/0805 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

摘要翻译： 半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。 这些电极分别连接到上电极布线和下电极。 当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在 上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。 因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

公开(公告)号：US06741192B2

公开(公告)日：2004-05-25

申请号：US10615391

申请日：2003-07-09

申请人： Kenji Murata ,  Daisuke Nomasaki

发明人： Kenji Murata ,  Daisuke Nomasaki

IPC分类号： H03M900

CPC分类号： H03M1/148 ,  H03M1/362

摘要： The present invention provides a serial/parallel A/D converter which is capable of performing a high-speed and high-accuracy operation even in the case where an analog input voltage Vin greatly varies in a period between a previous sampling period in which the analog input voltage is held and the next sampling period, when converting the analog input voltage Vin input into a digital value. This serial/parallel A/D converter includes a lower-order reference voltage initializing circuit 8 for initializing a lower-order reference voltage to an initialization voltage Vrc 23. The initialization voltage Vrc 23 is generated as the lower-order reference voltage in an arbitrary period from the start of sampling of the analog input voltage until the start of a comparison operation for the lower-order reference voltage, the value of the lower-order reference voltage is changed from the value of the initialization voltage to a voltage value which is decided on the basis of higher-order code selection signals P0C-P3C from a higher-order code selecting circuit 14, and the value of the lower-order reference voltage which is decided on the basis of the higher-order code selection signals P0C-P3C is compared with the value of the analog input voltage.

摘要翻译： 本发明提供一种串行/并行A / D转换器，其即使在模拟输入电压Vin在先前的采样周期之间的时段内大大变化的情况下也能够执行高速和高精度的操作，其中模拟 当将模拟输入电压Vin输入转换为数字值时，保持输入电压和下一个采样周期。 该串/并行A / D转换器包括用于将低阶参考电压初始化为初始化电压Vrc 23的低阶参考电压初始化电路8.初始化电压Vrc 23作为任意的低阶参考电压生成 从开始对模拟输入电压的采样开始到低阶参考电压的比较操作开始之间的时间段，将低阶参考电压的值从初始化电压的值改变为电压值，即， 基于来自高阶代码选择电路14的高阶代码选择信号P0C-P3C和基于较高阶代码选择信号P0C-P3C决定的低阶参考电压的值， P3C与模拟输入电压的值进行比较。

公开(公告)号：USD599785S1

公开(公告)日：2009-09-08

申请号：US29296666

申请日：2007-10-25

申请人： Takeshi Matsuda ,  Kenji Hatano ,  Masaji Komuro ,  Kenji Murata

设计人： Takeshi Matsuda ,  Kenji Hatano ,  Masaji Komuro ,  Kenji Murata

公开(公告)号：US06917856B2

公开(公告)日：2005-07-12

申请号：US10343913

申请日：2002-04-12

申请人： Kenji Murata

发明人： Kenji Murata

IPC分类号： B25J9/16 ,  B25J9/18 ,  B25J19/00 ,  G05B19/04 ,  G05B19/18

CPC分类号： B25J9/1674 ,  G05B2219/40218

摘要： It is constructed so as to detect a joint movement position of a robot arm by a position detector and a joint movement speed is calculated from change amounts of the joint movement position and elapsed time and is compared with an allowable movement speed and unlocking and locking of a brake are controlled so that the joint movement speed of an arm at the time of brake unlocking becomes within a constant value even when a shape, an attitude and a load condition of the robot arm vary. Therefore, movement work of the arm by the brake unlocking can be performed alone and a robot with high safety can be obtained.

摘要翻译： 其结构是通过位置检测器检测机器人手臂的关节运动位置，并且根据关节运动位置和经过时间的变化量计算关节运动速度，并将其与允许的运动速度进行比较并解锁和锁定 控制制动器，使得即使当机器人手臂的形状，姿态和负载条件变化时，制动器解锁时的臂的关节移动速度也变为恒定值。 因此，可以单独执行通过制动器解锁的臂的移动工作，并且可以获得具有高安全性的机器人。

公开(公告)号：US06771784B2

公开(公告)日：2004-08-03

申请号：US09926319

申请日：2002-01-09

申请人： Kenji Murata

发明人： Kenji Murata

IPC分类号： H03G500

CPC分类号： H04R1/26 ,  H04R3/04 ,  H04R3/14

摘要： A sub woofer system is constituted of a real time digital signal processing part 5 that includes an A/D converter 5a, a low pass filter block 5b, a delay block 5c, and a D/A converter block 5d, an analog power amplifier 6 and a speaker 7. The length of delay time of the delay block 5c is set so that the length of group delay time of the digital signal processing part 5 may equal an integral multiple of the length of time corresponding to one wavelength of the crossover point frequency between the digital signal processing part 5 and a main speaker 4. The signal processing is performed under the conditions that have been set as such. In this case, a construction is made up wherein the length of a group delay time produced in the digital type real time digital signal processing part can be set to a given value. By this construction, it is possible to provide a sub woofer system which can improve the phase interference between the main speaker and the sub woofer system at the crossover point between the two.

摘要翻译： 低音扬声器系统由包括A / D转换器5a，低通滤波器块5b，延迟块5c和D / A转换器块5d的实时数字信号处理部分5构成，模拟功率放大器6 和扬声器7.延迟块5c的延迟时间的长度被设置为使得数字信号处理部分5的组延迟时间的长度可以等于与交叉点的一个波长相对应的时间长度的整数倍 在数字信号处理部分5和主扬声器4之间的频率。信号处理在已被设置为这样的条件下执行。 在这种情况下，构成了数字型实时数字信号处理部中产生的群延迟时间的长度可以设定为给定值的结构。 通过这种结构，可以提供一种可以在两者之间的交叉点改善主扬声器和次低音扬声器系统之间的相位干扰的次低音扬声器系统。

公开(公告)号：US06667075B2

公开(公告)日：2003-12-23

申请号：US10110642

申请日：2002-04-12

申请人： Toshiaki Kitazoe ,  Keisuke Tanaka ,  Kenji Murata

发明人： Toshiaki Kitazoe ,  Keisuke Tanaka ,  Kenji Murata

IPC分类号： B05D310

CPC分类号： G02B1/18 ,  C03C17/245 ,  C03C17/3417 ,  C03C2217/213 ,  C03C2218/151 ,  C03C2218/152 ,  C03C2218/32 ,  C23C14/10 ,  C23C14/5853 ,  C23C16/0272 ,  C23C16/402 ,  C23C16/56 ,  G02B1/10

摘要： The present invention relates to a method for imparting hydrophilicity to a substrate whereby high hydrophilic properties and water-holding properties can be maintained for a long period of time. According to the present invention, an SiO2 film is formed directly or through an undercoat layer on a substrate under a reduced pressure of 100 Pa or less and immediately after the SiO2 film is formed, the SiO2 film is treated with water. Before forming the SiO2 film, it is also desirable that an undercoat layer consisting of a TiO2 film, Al2O3 film, Nb2O5 film, a laminated film prepared by laminating the TiO2 film on the Al2O3 film, a laminated film prepared by laminating the TiO2 film on the Nb2O5 film, or a low emissivity film be formed on a substrate and the SiO2 film be then formed on the undercoat film to serve as an SiO2 composite film.

公开(公告)号：US06218606B1

公开(公告)日：2001-04-17

申请号：US09404219

申请日：1999-09-23

申请人： Masashi Morizane ,  Toshio Yagiura ,  Kenji Murata ,  Takayoshi Yasuda ,  Nobuyuki Nishi

发明人： Masashi Morizane ,  Toshio Yagiura ,  Kenji Murata ,  Takayoshi Yasuda ,  Nobuyuki Nishi

IPC分类号： H01L31048

CPC分类号： H01L31/044 ,  H01L31/0201 ,  H01L31/048 ,  H01L31/0747 ,  Y02E10/50 ,  Y10S136/293

摘要： A plurality of solar cell groups having a plurality of solar cells connected to each other electrically in serial. A plurality of diodes are connected to each of the solar cell groups electrically in parallel. The plurality of diodes are sealed between transmissive front surface members and transmissive rear surface members together with the plurality of solar cell groups.

摘要翻译： 具有多个太阳能电池的多个太阳能电池组相互串联连接。 多个二极管并联电连接到每个太阳能电池组。 多个二极管与多个太阳能电池组一起被密封在透射前表面构件和透射后表面构件之间。