公开(公告)号：US06927723B2

公开(公告)日：2005-08-09

申请号：US10855397

申请日：2004-05-28

申请人： Daisuke Nomasaki ,  Kenji Murata ,  Hideki Tanaka ,  Yoshinori Miyada

发明人： Daisuke Nomasaki ,  Kenji Murata ,  Hideki Tanaka ,  Yoshinori Miyada

IPC分类号： H03M1/12 ,  H03M1/46

CPC分类号： H03M1/124 ,  H03M1/468

摘要： In a charge redistribution type A/D converter, an input-side capacitor terminal and a comparator-side capacitor terminal are connected through first and second analog switches to a fixed-voltage supply circuit, and the input-side capacitor terminal is connected through a third analog switch to the outside. Immediately before sampling an analog signal, the first and second analog switches are closed while the third analog switch is opened, according to a RESET signal. Thereby, fixed voltages are supplied to the input-side capacitor terminal and the comparator-side capacitor terminal, respectively, and charge stored in a weighting capacitor unit is initialized to a predetermined value.

摘要翻译： 在电荷再分配型A / D转换器中，输入侧电容器端子和比较器侧电容器端子通过第一和第二模拟开关连接到固定电压电源电路，并且输入侧电容器端子通过 第三个模拟开关到外面。 在采样模拟信号之前，根据RESET信号，第三模拟开关打开时，第一和第二模拟开关闭合。 由此，固定电压分别被提供给输入侧电容器端子和比较器侧电容器端子，并将存储在加权电容器单元中的电荷初始化为预定值。

公开(公告)号：US07777293B2

公开(公告)日：2010-08-17

申请号：US10898965

申请日：2004-07-27

申请人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

发明人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

IPC分类号： H01L29/93

CPC分类号： H01L27/0805 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

摘要翻译： 半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。 这些电极分别连接到上电极布线和下电极。 当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在 上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。 因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

公开(公告)号：US20050001291A1

公开(公告)日：2005-01-06

申请号：US10898965

申请日：2004-07-27

申请人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

发明人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/522 ,  H01L27/08 ,  H01L23/552

CPC分类号： H01L27/0805 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

摘要翻译： 半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。 这些电极分别连接到上电极布线和下电极。 当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在 上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。 因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

公开(公告)号：US06777775B2

公开(公告)日：2004-08-17

申请号：US10187378

申请日：2002-07-02

申请人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

发明人： Yoshinori Miyada ,  Kenji Murata ,  Daisuke Nomasaki

IPC分类号： H01L2900

CPC分类号： H01L27/0805 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

摘要翻译： 半导体集成电路具有多个电容器单元，并且每个电容器单元具有上电极和下电极。 这些电极分别连接到上电极布线和下电极。 当例如上电极连接到上电极布线并且电极布线位于另一个电容器单元的下电极的一侧或连接这些电极的下电极布线的一侧时，屏蔽布线设置在 上电极布线和另一个电容器单元的相邻位置的下电极或上电极布线和相邻位置的下电极布线之间。 因此，利用该屏蔽布线，可以有效地抑制电容器单元的各布线与电容器单元的每个上电极或每个下电极之间的电容耦合。

公开(公告)号：US06741192B2

公开(公告)日：2004-05-25

申请号：US10615391

申请日：2003-07-09

申请人： Kenji Murata ,  Daisuke Nomasaki

发明人： Kenji Murata ,  Daisuke Nomasaki

IPC分类号： H03M900

CPC分类号： H03M1/148 ,  H03M1/362

摘要： The present invention provides a serial/parallel A/D converter which is capable of performing a high-speed and high-accuracy operation even in the case where an analog input voltage Vin greatly varies in a period between a previous sampling period in which the analog input voltage is held and the next sampling period, when converting the analog input voltage Vin input into a digital value. This serial/parallel A/D converter includes a lower-order reference voltage initializing circuit 8 for initializing a lower-order reference voltage to an initialization voltage Vrc 23. The initialization voltage Vrc 23 is generated as the lower-order reference voltage in an arbitrary period from the start of sampling of the analog input voltage until the start of a comparison operation for the lower-order reference voltage, the value of the lower-order reference voltage is changed from the value of the initialization voltage to a voltage value which is decided on the basis of higher-order code selection signals P0C-P3C from a higher-order code selecting circuit 14, and the value of the lower-order reference voltage which is decided on the basis of the higher-order code selection signals P0C-P3C is compared with the value of the analog input voltage.

摘要翻译： 本发明提供一种串行/并行A / D转换器，其即使在模拟输入电压Vin在先前的采样周期之间的时段内大大变化的情况下也能够执行高速和高精度的操作，其中模拟 当将模拟输入电压Vin输入转换为数字值时，保持输入电压和下一个采样周期。 该串/并行A / D转换器包括用于将低阶参考电压初始化为初始化电压Vrc 23的低阶参考电压初始化电路8.初始化电压Vrc 23作为任意的低阶参考电压生成 从开始对模拟输入电压的采样开始到低阶参考电压的比较操作开始之间的时间段，将低阶参考电压的值从初始化电压的值改变为电压值，即， 基于来自高阶代码选择电路14的高阶代码选择信号P0C-P3C和基于较高阶代码选择信号P0C-P3C决定的低阶参考电压的值， P3C与模拟输入电压的值进行比较。

公开(公告)号：US07884750B2

公开(公告)日：2011-02-08

申请号：US12643613

申请日：2009-12-21

申请人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

发明人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

IPC分类号： H03M1/38

CPC分类号： H03M1/168

摘要： In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.

摘要翻译： A / D变换电路101具备A / D转换电路101，用于对输入信号进行运算放大并输出放大信号，A / D变换电路101除了具有放大器1a以外还包括初始值设定电路4a A / D转换器2a，子D / A转换器3a和电容器C11和C12。 为了确保放大器1a的输出电压的初始值为放大器1a在工作放大开始时接近于工作放大的目标值的给定电压值，初始值设定电路4a施加给定的偏置值 等于接近目标值的给定电压值连接到放大器1a的输出侧的下一级电容器C13。 在流水线A / D转换器的各阶段使用能够对运算放大的目标值进行快速收敛的A / D转换电路101。

公开(公告)号：US20090040088A1

公开(公告)日：2009-02-12

申请号：US11631844

申请日：2006-03-24

申请人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

发明人： Toshiaki Ozeki ,  Daisuke Nomasaki ,  Koji Oka

IPC分类号： H03M1/38

CPC分类号： H03M1/168

摘要： In an A/D converter provided with an A/D converter circuit 101 for operationally amplifying an input signal and outputting an amplified signal, the A/D converter circuit 101 includes an initial value setting circuit 4a in addition to an amplifier 1a, a sub-A/D converter 2a, a sub-D/A converter 3a and capacitors C11 and C12. To ensure that the initial value of the output voltage of the amplifier 1a is a given voltage value close to the target value of operational amplification at the start of the operational amplification by the amplifier 1a, the initial value setting circuit 4a applies a given bias value equal to the given voltage value close to the target value to a next-stage capacitor C13 to be connected to the output side of the amplifier 1a. Such an A/D converter circuit 101 that can perform speedy convergence to the target value of operational amplification is used at each stage of a pipeline A/D converter.

摘要翻译： A / D变换电路101具备A / D转换电路101，用于对输入信号进行运算放大并输出放大信号，A / D变换电路101除了具有放大器1a以外还包括初始值设定电路4a A / D转换器2a，子D / A转换器3a和电容器C11和C12。 为了确保放大器1a的输出电压的初始值为放大器1a在工作放大开始时接近于工作放大的目标值的给定电压值，初始值设定电路4a施加给定的偏置值 等于接近目标值的给定电压值连接到放大器1a的输出侧的下一级电容器C13。 在流水线A / D转换器的各阶段使用能够对运算放大的目标值进行快速收敛的A / D转换电路101。

公开(公告)号：US20110254125A1

公开(公告)日：2011-10-20

申请号：US12600094

申请日：2008-05-16

申请人： Daisuke Nomasaki ,  Koji Oka ,  Toshiaki Ozeki

发明人： Daisuke Nomasaki ,  Koji Oka ,  Toshiaki Ozeki

IPC分类号： H01L27/00

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2224/05553 ,  H01L2224/06 ,  H01L2924/0002 ,  H03H11/04 ,  H03H2001/0014 ,  H03L7/0891 ,  H03L7/093 ,  H01L2924/00

摘要： A semiconductor integrated circuit according to the present invention is equipped with a plurality of analog macros having comb capacitors (10), each comb capacitor (10) has a comb-shaped first electrode (11) and a comb-shaped second electrode (12), comb tooth portions (13) of the electrode (11) and comb tooth portions (14) of the electrode (12) are engaged so that the comb tooth portions (13) and the comb tooth portions (14) are arranged alternately and parallel to one another, and a comb tooth interval S of the comb capacitor is varied according to an absolute accuracy indicating an error between an actual capacitance value and an ideal capacitance value, or a relative accuracy indicating a difference in capacitance values between adjacent comb capacitors. Thereby, it is possible to provide a semiconductor integrated circuit which is equipped with highly-accurate analog macros and highly-integrated analog macros having comb capacitors which ensure high capacitance accuracies.

摘要翻译： 根据本发明的半导体集成电路配备有具有梳状电容器（10）的多个模拟宏，每个梳状电容器（10）具有梳状的第一电极（11）和梳状的第二电极（12） 电极（11）的梳齿部（13）和电极（12）的梳齿部（14）接合，使得梳齿部（13）和梳齿部（14）交替平行配置 并且梳状电容器的梳齿间隔S根据指示实际电容值和理想电容值之间的误差的绝对精度或指示相邻梳状电容器之间的电容值差的相对精度而变化。 因此，可以提供一种半导体集成电路，其配备有高精度模拟宏和具有确保高电容精度的梳状电容器的高度集成的模拟宏。

公开(公告)号：US06734817B2

公开(公告)日：2004-05-11

申请号：US10328159

申请日：2002-12-26

申请人： Junichi Naka ,  Yoshitsugu Inagaki ,  Hiroshi Sakura ,  Heiji Ikoma ,  Koji Oka ,  Youichi Okamoto ,  Daisuke Nomasaki

发明人： Junichi Naka ,  Yoshitsugu Inagaki ,  Hiroshi Sakura ,  Heiji Ikoma ,  Koji Oka ,  Youichi Okamoto ,  Daisuke Nomasaki

IPC分类号： H03M112

CPC分类号： H03M1/002 ,  H03M1/007 ,  H03M1/12

摘要： When the performance of an A/D converter required by a system changes, power consumption of the overall system can be reduced. The resolution of an A/D converter is made variable by changing a current flowing through an amplifier by an external control signal that specifies the resolution. Thus, when the performance required by a system changes, it is possible to change the performance of the A/D converter and to prevent a performance overhead of the A/D converter. Consequently, power consumption of the A/D converter is reduced, and power consumption of the system as a whole is also reduced.

摘要翻译： 当系统所需的A / D转换器的性能改变时，可以降低整个系统的功耗。 通过用指定分辨率的外部控制信号改变流过放大器的电流，可以使A / D转换器的分辨率可变。 因此，当系统所需的性能改变时，可以改变A / D转换器的性能并且防止A / D转换器的性能开销。 因此，A / D转换器的功耗降低，整个系统的功耗也降低。

公开(公告)号：US20100188151A1

公开(公告)日：2010-07-29

申请号：US12445003

申请日：2008-07-30

申请人： Daisuke Nomasaki ,  Koji Oka

发明人： Daisuke Nomasaki ,  Koji Oka

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H01L27/0629 ,  H01L27/0811 ,  H01L27/088 ,  H03F2203/45352 ,  H03F2203/45371 ,  H03F2203/45486 ,  H03M1/0682 ,  H03M1/0695 ,  H03M1/442

摘要： A differential voltage interconnect (W101a) electrically connects the gate electrode of a transistor to be used among differential transistors (T101a, T101a, . . . ) to an input node receiving an input voltage (Vinn), and a differential voltage interconnect (W101b) electrically connects the gate electrode of a transistor to be used among differential transistors (T101b, T101b, . . . ) to an input node receiving an input voltage (Vinp). A bias voltage interconnect (W102) electrically connects the gate electrode of a transistor to be used among current source transistors (T102, T102, . . . ) to a bias node receiving a bias voltage (VBN), and a bias voltage interconnect (W103) electrically connects the gate electrodes of transistors to be used among load transistors (T103a, T103a, T103b, T103b, . . . ) to a bias node receiving a bias voltage (VBP).

摘要翻译： 差分电压互连（W101a）将要用于差分晶体管（T101a，T101a ...等）的晶体管的栅极电连接到接收输入电压（Vinn）的输入节点和差分电压互连（W101b） 将待使用的晶体管的栅电极（T101b，T101b ...）电连接到接收输入电压（Vinp）的输入节点。 偏置电压互连（W102）将要用于电流源晶体管（T102，T102 ......）中的晶体管的栅极电连接到接收偏置电压（VBN）的偏置节点和偏置电压互连（W103 ）将负载晶体管（T103a，T103a，T103b，T103b ...等）中使用的晶体管的栅极电连接到接收偏置电压（VBP）的偏置节点。