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公开(公告)号：US5373712A
公开(公告)日：1994-12-20
申请号：US124215
申请日：1993-09-21
CPC分类号： D04B21/02 , A44B18/0034 , D04B21/10 , D10B2501/0632 , Y10T24/2775
摘要： A warp-knit cloth for a surface fastener, comprising: a foundation design knitted of pile knitting yarns and foundation yarns so as to form pile loops, which serve as engaging elements of the surface fastener, on wales; a marquisette design in which inlaid yarn extend in the wale direction and course direction so as to form squared meshes, which serve as vents, between said wales.
摘要翻译： 一种用于表面紧固件的经编织物，包括：由编织纱线和基础纱线编织的基础设计，以形成用作表面紧固件的接合元件的绳索，在纵行上; 镶嵌纱线沿着纵行方向和方向延伸，以便在所述威尔士之间形成用作通风口的平方网格。
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公开(公告)号：US4838044A
公开(公告)日：1989-06-13
申请号：US172270
申请日：1988-03-22
CPC分类号： D04B21/02 , A44B18/0034 , D10B2501/0632
摘要： A warp-knit tape is disclosed for use in hook-and-loop fasteners, which tape comprises a pile portion and selvage portions on opposite sides thereof, the pile portion including pile-loops arranged to extend longitudinally in a meandering fashion to prevent the same from tilting down flat on the surface of the tape.
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公开(公告)号：US07725847B2
公开(公告)日：2010-05-25
申请号：US10586908
申请日：2004-11-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/05554 , H01L2224/32145 , H01L2224/48095 , H01L2224/48227 , H01L2224/49052 , H01L2224/49171 , H01L2224/85 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A design support apparatus supports wiring design for bond wires that connect a semiconductor chip and an interposer. The design support apparatus includes a creating unit that creates simulated design data simulating occurrence of fluctuation in an arrangement position of a semiconductor chip on an interposer and occurrence of fluctuation in bond wire connection terminal positions of the interposer, and an analyzing unit that analyzes, based on the simulated design data, deficiencies in manufacturing of semiconductor devices due to the fluctuation in the arrangement position of the semiconductor chip on the interposer and the fluctuation in the bond wire connection terminal positions of the interposer.
摘要翻译： 设计支持设备支持连接半导体芯片和插入器的接合线的布线设计。 设计支持装置包括：创建单元，其创建模拟设计数据，模拟在插入器上的半导体芯片的布置位置的波动的发生以及插入器的接合线连接端子位置的波动的发生;以及分析单元， 关于模拟设计数据，由于插入件上的半导体芯片的布置位置的波动以及插入器的接合线连接端子位置的波动引起的半导体器件的制造缺陷。
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公开(公告)号：US07240521B2
公开(公告)日：2007-07-10
申请号：US11384902
申请日：2006-03-20
申请人： Yoshio Matsuda
发明人： Yoshio Matsuda
IPC分类号： D04B21/20
CPC分类号： A44B19/343 , A44B19/56 , D04B21/16 , D10B2501/0631
摘要： A knitted-in slide fastener in which a continuous fastener element row can be mounted stably in its dimensional meaning and firmly while breaking of a needle is prevented, so as to secure a smooth engagement of elements, wherein the continuous fastener element row is fixed and knitted-in by a fixing chain knitting yarn at the same time when a fastener tape is knitted, the fixing chain knitting yarn for the elements is knitted into plural wales of a fastener element attaching portion on one side edge of the fastener tape, warp knitting yarns to be knitted for reinforcement are entangled with a needle loop formed by a constituent yarn of at least one of wales in a foundation structure adjoining the plural wales through their needle loops but not entangled with a needle loop of the fixing chain knitting yarn through their needle loops.
摘要翻译： 一种编织的拉链，其中防止连续的拉链牙列在其尺寸意义上稳定地被安装并且在破裂时牢固地被安装，以便确保连续的拉链牙排固定的元件的平滑接合， 在编织拉链带的同时通过固定链编织纱编织，用于元件的固定链编织纱被编织成拉链带的一个侧边缘上的拉链牙齿附着部分的多个纵行，经编 用于加强的针织纱线与通过其针环相邻的多个纵行的基础结构中的至少一个纵行的组成纱线形成的针环缠绕，但是没有与固定链编织纱线的针环缠结通过它们 针环。
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公开(公告)号：US06651296B2
公开(公告)日：2003-11-25
申请号：US10155784
申请日：2002-05-24
申请人： Yoshio Matsuda
发明人： Yoshio Matsuda
IPC分类号： A44B1956
CPC分类号： A44B19/343 , D04B21/16 , D10B2501/0631 , Y10T24/252 , Y10T24/2523 , Y10T24/2527 , Y10T24/2529
摘要： There is provided a knit-in slide fastener in which a continuous fastener element row is knitted simultaneously with the knitting of a warp knitted fastener tape at a fastener element mounting portion on a longitudinal side edge portion of the fastener tape. Since a yarn composed of ordinary long fibers, or a textured yarn is employed as a fixing knitting yarn for the fastener element mounting portion, even if a sewing needle is pierced into the textured yarn, the fixing knitting yarn is never cut off because the sewing needle passes through a number of fibers which compose the textured yarn. Further, even when part of the fibers are cut off, no fraying occurs in the yarns, so that the fastener element row at the cut off portions does not separate from the fastener tape.
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公开(公告)号：US06404691B1
公开(公告)日：2002-06-11
申请号：US08472770
申请日：1995-06-07
IPC分类号： G11C700
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.
摘要翻译： 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。
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公开(公告)号：US6075732A
公开(公告)日：2000-06-13
申请号：US334917
申请日：1999-06-17
IPC分类号： G11C11/413 , G11C7/00 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L27/10
CPC分类号： G11C29/806 , G11C29/781 , G11C8/10
摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
摘要翻译： 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）中存在缺陷行时产生备用行解码器选择信号（+ E，ovs SRE + EE） ），并且由行解码器组（4a，4b）选择有缺陷的行。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（+ E，ovs SRE + EE）和块控制信号被激活。
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8.发明授权
公开(公告)号：US5685177A
公开(公告)日：1997-11-11
申请号：US649077
申请日：1996-05-16
申请人： Yoshio Matsuda , Hidenobu Kato , Yoshito Ikeguchi
发明人： Yoshio Matsuda , Hidenobu Kato , Yoshito Ikeguchi
CPC分类号： A44B19/343 , D04B21/16 , D10B2501/0631
摘要： In a knit slide fastener in which a continuous fastener element row is knitted in a fastener element attaching portion of each fastener tape simultaneously with the knitting of the fastener tape, a plurality of laid-in weft yarns are knitted in the warp-knit structure of the fastener element attaching portion so as to turn alternately in every course and to be interlaced with knit loops of a chain stitch extending along the outermost edge of the fastener element attaching portion, and the fastener element row is secured to the ground structure of the attaching portion by two binding chain stitches.
摘要翻译： 在针织拉链中，连续的拉链牙排与拉链带的编织同时编织在每个拉链带的拉链牙固定部分中，多根纬纱以经编针织结构编织 所述紧固件元件安装部分在每个路线中交替地转动并且与沿所述拉链件附接部分的最外边缘延伸的链式线迹的编织圈交错，并且所述拉链件排固定到所述连接件的接地结构 部分通过两个绑定链式线迹。
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公开(公告)号：US5586369A
公开(公告)日：1996-12-24
申请号：US520857
申请日：1995-08-30
申请人： Yoshio Matsuda , Shunji Akashi , Hiroshi Yoshida
发明人： Yoshio Matsuda , Shunji Akashi , Hiroshi Yoshida
CPC分类号： A44B19/34 , Y10T24/25 , Y10T24/252 , Y10T24/2521
摘要： A slide fastener tape woven or knitted so as to form a coupling element attaching edge portion, a tape body portion and a tape sewing portion arranged in order transversely of the tape, wherein the tape has a double-layer structure portion composed of a front cloth and a back cloth joined together by a connecting yarn with a predetermined gap therebetween extending transversely over a predetermined region of the tape, the connecting yarn being a synthetic resin monofilament or multifilament, the back cloth of the double-layer structure portion being a section formed of at least a mesh woven or knitted fabric.
摘要翻译： 一种拉链带，其编织或编织以形成连接件附接边缘部分，带体部分和带状缝合部分，其横向于所述带布置，其中所述带具有由前布构成的双层结构部分 以及通过连接纱线以预定的间隙横向延伸超过所述带的预定区域的连接纱线的后布，所述连接纱线是合成树脂单丝或复丝，所述双层结构部分的背布是形成的部分 的至少一个网织物或针织物。
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公开(公告)号：US5504713A
公开(公告)日：1996-04-02
申请号：US180166
申请日：1994-01-11
CPC分类号： G11C29/806 , G11C29/781
摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
摘要翻译： 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）和缺陷行中存在缺陷行时产生备用行解码器选择信号（＆amp; upbar＆S） 由行解码器组（4a，4b）选择。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（＆amp; S＆amp; S）和块控制信号被激活。
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