公开(公告)号：US5933726A

公开(公告)日：1999-08-03

申请号：US709203

申请日：1996-08-27

申请人： Michio Nishimura ,  Kazuhiko Saitoh ,  Masayuki Yasuda ,  Takashi Hayakawa ,  Michio Tanaka ,  Yuji Ezaki ,  Katsuo Yuhara ,  Minoru Ohtsuka ,  Toshikazu Kumai ,  Songsu Cho ,  Toshiyuki Kaeriyama ,  Keizo Kawakita ,  Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Jun Murata ,  Hideo Aoki ,  Akihiko Konno ,  Kiyomi Katsuyama ,  Takafumi Tokunaga ,  Yoshimi Torii

发明人： Michio Nishimura ,  Kazuhiko Saitoh ,  Masayuki Yasuda ,  Takashi Hayakawa ,  Michio Tanaka ,  Yuji Ezaki ,  Katsuo Yuhara ,  Minoru Ohtsuka ,  Toshikazu Kumai ,  Songsu Cho ,  Toshiyuki Kaeriyama ,  Keizo Kawakita ,  Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Jun Murata ,  Hideo Aoki ,  Akihiko Konno ,  Kiyomi Katsuyama ,  Takafumi Tokunaga ,  Yoshimi Torii

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

摘要翻译： 诸如动​​态RAM的半导体器件及其制造方法。 在p型硅衬底（1）的顶部上沿着取向方向以规定的间隔放置多个堆叠的电池电容器。 每个电容器具有几乎垂直的圆柱形下电极（圆柱形多晶硅层（96）），电介质膜（氮化硅膜（77））和上电极（由多晶硅制成的板电极（78））。 排列方向上的间隔小于下电极的内径。

公开(公告)号：US5972862A

公开(公告)日：1999-10-26

申请号：US901475

申请日：1997-07-28

申请人： Yoshimi Torii ,  Shunji Sasabe ,  Masayuki Kojima ,  Kazuhisa Usuami ,  Takafumi Tokunaga ,  Kazusato Hara ,  Yoshikazu Ohira ,  Tsuyoshi Matsui ,  Hideto Gotoh ,  Tetsuo Aoyama ,  Ryuji Hasemi ,  Hidetoshi Ikeda ,  Fukusaburo Ishihara ,  Ryuji Sotoaka

发明人： Yoshimi Torii ,  Shunji Sasabe ,  Masayuki Kojima ,  Kazuhisa Usuami ,  Takafumi Tokunaga ,  Kazusato Hara ,  Yoshikazu Ohira ,  Tsuyoshi Matsui ,  Hideto Gotoh ,  Tetsuo Aoyama ,  Ryuji Hasemi ,  Hidetoshi Ikeda ,  Fukusaburo Ishihara ,  Ryuji Sotoaka

IPC分类号： C11D7/60 ,  G03F7/42 ,  H01L21/02 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3213 ,  C11D1/62 ,  C11D3/44 ,  C11D7/08

CPC分类号： H01L21/02071 ,  G03F7/423 ,  G03F7/425 ,  H01L21/02063 ,  Y10S438/974

摘要： There is disclosed a cleaning liquid for producing a semiconductor device which comprises (A) fluorine-containing compound; (B) water-soluble or water-miscible organic solvent; and (C) inorganic acid and/or organic acid, optionally, further comprises (D) quaternary ammonium salt or (D') a specific organic carboxylic acid ammonium salt and/or an organic carboxylic acid amine salt; as well as a process for producing a semiconductor device by forming a resist pattern on a substrate equipped on the surface with an insulating film layer or a metallic electroconductive layer, forming a via hole or electric wiring by dry etching, removing the resist pattern by ashing treatment with oxygen plasma; and effecting an cleaning treatment with the above cleaning liquid. The above cleaning liquid and production process can readily remove the deposit polymer formed in the case of dry etching without impairing metallic film and insulating film.

摘要翻译： 公开了一种用于制造半导体器件的清洗液，其包含（A）含氟化合物; （B）水溶性或水混溶性有机溶剂; 和（C）无机酸和/或有机酸，任选地还包含（D）季铵盐或（D'）特定的有机羧酸铵盐和/或有机羧酸胺盐; 以及通过在表面上配置有绝缘膜层或金属导电层的基板上形成抗蚀剂图案来制造半导体器件的方法，通过干蚀刻形成通孔或电布线，通过灰化除去抗蚀剂图案 用氧等离子体处理; 并用上述清洗液进行清洗处理。 上述清洗液和制造方法可以容易地除去在干蚀刻的情况下形成的沉积聚合物，而不损害金属膜和绝缘膜。

公开(公告)号：US06791137B2

公开(公告)日：2004-09-14

申请号：US10396339

申请日：2003-03-26

申请人： Satoru Yamada ,  Kiyonori Oyu ,  Takafumi Tokunaga ,  Hiroyuki Enomoto ,  Toshihiro Sekiguchi

发明人： Satoru Yamada ,  Kiyonori Oyu ,  Takafumi Tokunaga ,  Hiroyuki Enomoto ,  Toshihiro Sekiguchi

IPC分类号： H01L2972

CPC分类号： H01L27/10888 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10891 ,  H01L28/90 ,  Y10S257/906

摘要： In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing the capacity for a word line formed over the gate electrode (word line). By setting the level of the upper end of the side wall insulating film made of silicon oxide to be lower than that of the top face of a cap insulating film, the diameter in the upper part of a plug buried in each space (contact holes) between the gate electrodes is set larger than the diameter in the bottom part to assure a contact area between the contact hole and a through hole formed on the contact hole.

摘要翻译： 在具有精细存储单元和位线容量降低的半导体集成电路器件中，栅电极（字线）的侧壁绝缘膜由氮化硅和氧化硅的侧壁绝缘膜制成，其介电常数小于 由氮化硅制成的侧壁绝缘膜，从而降低在栅电极（字线）上形成的字线的容量。 通过将由氧化硅构成的侧壁绝缘膜的上端的高度设定为低于帽绝缘膜的顶面的上端的高度，埋入各空间（接触孔）的插头的上部的直径， 栅电极之间的距离设定为大于底部的直径，以确保接触孔与形成在接触孔上的通孔之间的接触面积。

公开(公告)号：US06555861B2

公开(公告)日：2003-04-29

申请号：US09765574

申请日：2001-01-22

申请人： Satoru Yamada ,  Kiyonori Oyu ,  Takafumi Tokunaga ,  Hiroyuki Enomoto ,  Toshihiro Sekiguchi

发明人： Satoru Yamada ,  Kiyonori Oyu ,  Takafumi Tokunaga ,  Hiroyuki Enomoto ,  Toshihiro Sekiguchi

IPC分类号： H01L2972

CPC分类号： H01L27/10888 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10891 ,  H01L28/90 ,  Y10S257/906

摘要： In semiconductor integrated circuit devices having fine memory cells and a reduced bit line capacity, a side wall insulating film of gate electrodes (word line) is made of silicon nitride and a side wall insulating film of silicon oxide having a dielectric constant smaller than that of the side wall insulating film made of silicon nitride, thereby reducing the capacity for a word line formed over the gate electrode (word line). By setting the level of the upper end of the side wall insulating film made of silicon oxide to be lower than that of the top face of a cap insulating film, the diameter in the upper part of a plug buried in each space (contact holes) between the gate electrodes is set larger than the diameter in the bottom part to assure a contact area between the contact hole and a through hole formed on the contact hole.

摘要翻译： 在具有精细存储单元和位线容量降低的半导体集成电路器件中，栅电极（字线）的侧壁绝缘膜由氮化硅和氧化硅的侧壁绝缘膜制成，其介电常数小于 由氮化硅制成的侧壁绝缘膜，从而降低在栅电极（字线）上形成的字线的容量。 通过将由氧化硅构成的侧壁绝缘膜的上端的高度设定为低于帽绝缘膜的顶面的上端的高度，埋入各空间（接触孔）的插头的上部的直径， 栅电极之间的距离设定为大于底部的直径，以确保接触孔与形成在接触孔上的通孔之间的接触面积。

公开(公告)号：US20060292791A1

公开(公告)日：2006-12-28

申请号：US11513369

申请日：2006-08-31

申请人： Takafumi Tokunaga ,  Makoto Yoshida ,  Fumio Ootsuka

发明人： Takafumi Tokunaga ,  Makoto Yoshida ,  Fumio Ootsuka

IPC分类号： H01L21/8242 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L27/10894 ,  H01L21/823814 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10873

摘要： In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.

公开(公告)号：US20050186801A1

公开(公告)日：2005-08-25

申请号：US11104441

申请日：2005-04-13

申请人： Shouochi Uno ,  Atsushi Maekawa ,  Takashi Yunogami ,  Kazutami Tago ,  Kazuo Nojiri ,  Shuntaro Machida ,  Takafumi Tokunaga

发明人： Shouochi Uno ,  Atsushi Maekawa ,  Takashi Yunogami ,  Kazutami Tago ,  Kazuo Nojiri ,  Shuntaro Machida ,  Takafumi Tokunaga

IPC分类号： H01L21/3065 ,  H01L21/311 ,  H01L21/312 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/02126 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3122 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829 ,  H01L21/76835

摘要： In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.

摘要翻译： 在制造具有嵌入式互连结构的半导体集成电路器件的方法中，通过将导体膜嵌入形成在构成层间电介质膜的有机绝缘膜中的凹槽（例如沟槽或孔）中，并且包括有机硅氧烷作为 通过使有机绝缘膜在基于CF的气体/ N 2 / Ar气中进行等离子体干蚀刻来形成主要部件，凹槽，例如沟槽或孔，以便抑制 在凹陷的底部形成异常形状，在有机绝缘膜上形成光致抗蚀剂膜，然后用光致抗蚀剂膜作为蚀刻掩模形成凹部。

公开(公告)号：US06660647B1

公开(公告)日：2003-12-09

申请号：US09646012

申请日：2001-01-11

申请人： Tetsuo Ono ,  Takafumi Tokunaga ,  Tadashi Umezawa ,  Motohiko Yoshigai ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takashi Sato ,  Yasushi Goto

发明人： Tetsuo Ono ,  Takafumi Tokunaga ,  Tadashi Umezawa ,  Motohiko Yoshigai ,  Tatsumi Mizutani ,  Tokuo Kure ,  Masayuki Kojima ,  Takashi Sato ,  Yasushi Goto

IPC分类号： H01L2100

CPC分类号： H01J37/32082 ,  H01L21/32136 ,  H01L21/32139

摘要： A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.

摘要翻译： 具有在被处理物质上形成的不含有碳作为主要成分的掩模层的样品的表面处理方法，该物质是沉积在硅基板上的金属，半导体和绝缘体，该物质包括如下步骤： 在真空容器中的样品板上，在真空容器内产生由卤素气体和粘合气体的混合物构成的等离子体，在样品板上施加频率范围为200kHz〜20MHz的射频偏置电压， 以从100Hz到10kHz的开关控制频率来控制射频偏置电压的周期性的断开。

公开(公告)号：US20050070099A1

公开(公告)日：2005-03-31

申请号：US10989260

申请日：2004-11-17

申请人： Takafumi Tokunaga ,  Makoto Yoshida ,  Fumio Ootsuka

发明人： Takafumi Tokunaga ,  Makoto Yoshida ,  Fumio Ootsuka

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/44 ,  H01L21/8234

CPC分类号： H01L27/10894 ,  H01L21/823814 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10873

摘要： In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.

摘要翻译： 在具有DRAM和逻辑集成电路混合安装在芯片上的具有片上系统结构的半导体集成电路器件中，在直接的MISFET的源极和漏极的表面上形成硅化物层 DRAM的外围电路，DRAM的间接外围电路的MISFET的源极和漏极的表面以及逻辑集成电路的MISFET的源极和漏极的表面以及硅化物层不是 形成在DRAM的存储单元的存储单元选择性MISFET的源极和漏极的表面上。

公开(公告)号：US06838320B2

公开(公告)日：2005-01-04

申请号：US09970664

申请日：2001-10-05

申请人： Takafumi Tokunaga ,  Makoto Yoshida ,  Fumio Ootsuka

发明人： Takafumi Tokunaga ,  Makoto Yoshida ,  Fumio Ootsuka

IPC分类号： H01L21/8242 ,  H01L21/82 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L27/10894 ,  H01L21/823814 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10873

摘要： In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.

摘要翻译： 在具有DRAM和逻辑集成电路混合安装在芯片上的具有片上系统结构的半导体集成电路器件中，在直接的MISFET的源极和漏极的表面上形成硅化物层 DRAM的外围电路，DRAM的间接外围电路的MISFET的源极和漏极的表面以及逻辑集成电路的MISFET的源极和漏极的表面以及硅化物层不是 形成在DRAM的存储单元的存储单元选择性MISFET的源极和漏极的表面上。

公开(公告)号：US06767838B1

公开(公告)日：2004-07-27

申请号：US09691119

申请日：2000-10-19

申请人： Tetsuo Ono ,  Tatsumi Mizutani ,  Ryouji Hamasaki ,  Tokuo Kure ,  Takafumi Tokunaga ,  Masayuki Kojima

发明人： Tetsuo Ono ,  Tatsumi Mizutani ,  Ryouji Hamasaki ,  Tokuo Kure ,  Takafumi Tokunaga ,  Masayuki Kojima

IPC分类号： H01L2128

CPC分类号： H01J37/32137 ,  C23F4/00 ,  H01J37/32706 ,  H01L21/32137

摘要： A method and apparatus of treating a surface of a sample. A sample is arranged on a stage provided in a chamber, an etching gas is continuously supplied into the chamber and a plasma is generated from the etching gas. An rf bias at a frequency of 100 kHz or higher is applied to the stage independently of the generation of the plasma, and the rf bias is modulated at a frequency of 100 Hz to 10 kHz. Thereby, a surface treatment in which a minimum feature size is 1 &mgr;m or smaller is performed on the sample.

摘要翻译： 一种处理样品表面的方法和装置。 将样品布置在设置在室中的台上，将蚀刻气体连续地供应到室中，并从蚀刻气体产生等离子体。 频率为100kHz或更高的rf偏置与等离子体的产生无关地施加到载物台，并且以100Hz至10kHz的频率调制rf偏置。 由此，对样本进行最小特征尺寸为1μm以下的表面处理。