公开(公告)号：US20070018822A1

公开(公告)日：2007-01-25

申请号：US11413182

申请日：2006-04-28

申请人： Young-jin Lee ,  Dong-won Kim

发明人： Young-jin Lee ,  Dong-won Kim

IPC分类号： G08B13/14

CPC分类号： G08B27/008 ,  G08B27/006

摘要： A digital TV system for forwarding EAS information and a method thereof are provided. The digital TV system forwards the EAS information to an external device including a mobile phone. Accordingly, even if a user does not watch the TV or does something different from watching the TV, the user can easily obtain the EAS information through his/her own mobile phone and promptly cope with an emergency situation.

摘要翻译： 提供了一种用于转发EAS信息的数字电视系统及其方法。 数字电视系统将EAS信息转发到包括移动电话的外部设备。 因此，即使用户不观看电视机或者观看电视机也不同，用户可以通过自己的手机轻松获取EAS信息，并及时应对紧急情况。

公开(公告)号：US20100059807A1

公开(公告)日：2010-03-11

申请号：US12461500

申请日：2009-08-13

申请人： Keun-hwl Cho ,  Dong-won Kim ,  Jun Seo ,  Min-sang Kim ,  Sung-min Kim ,  Hyun-jun Bae ,  Ji-Myoung Lee

发明人： Keun-hwl Cho ,  Dong-won Kim ,  Jun Seo ,  Min-sang Kim ,  Sung-min Kim ,  Hyun-jun Bae ,  Ji-Myoung Lee

IPC分类号： H01L27/108

CPC分类号： H01L29/66795 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10879 ,  H01L29/785

摘要： A semiconductor device having a bar type active pattern and a method of manufacturing the same are provided. The semiconductor device may include a semiconductor substrate having a semiconductor fin configured to protrude from a surface of the semiconductor substrate in a first direction, the semiconductor substrate having a first width and a second width crossing the first width, wherein the first width and the second width extend in a second direction. A plurality of active patterns may be arranged in the first direction with a separation gap from the semiconductor fin. A plurality of support patterns may be arranged between the semiconductor fin and one of the plurality of active patterns arranged closer to the semiconductor fin in the first direction, and between the plurality of active patterns arranged in the first direction to support the plurality of active patterns. A gate may be arranged to cross the plurality of active patterns in the second direction and to cover a portion of the at least one of the plurality of active patterns.

摘要翻译： 提供了具有条形有源图案的半导体器件及其制造方法。 半导体器件可以包括具有半导体鳍片的半导体衬底，半导体鳍片被配置为在第一方向上从半导体衬底的表面突出，半导体衬底具有与第一宽度交叉的第一宽度和第二宽度，其中第一宽度和第二宽度 宽度在第二方向上延伸。 多个有源图案可以在第一方向上与半导体鳍片分离间隙布置。 多个支撑图案可以布置在半导体翅片与沿着第一方向布置得更靠近半导体鳍片的多个有源图案中的一个之间以及沿着第一方向布置的多个有源图案之间，以支撑多个有源图案 。 栅极可以布置成在第二方向上跨越多个有源图案并且覆盖多个有源图案中的至少一个的一部分。

公开(公告)号：US07618864B2

公开(公告)日：2009-11-17

申请号：US11589178

申请日：2006-10-30

申请人： Chang-woo Oh ,  Sung-hwan Kim ,  Dong-gun Park ,  Dong-won Kim

发明人： Chang-woo Oh ,  Sung-hwan Kim ,  Dong-gun Park ,  Dong-won Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/7887

摘要： Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase.

摘要翻译： 示例性实施例涉及半导体存储器件及其形成方法。 其他示例实施例涉及非易失性存储器件及其形成方法。 存储器件可以包括分别形成在形成在衬底上的杂质区域之间的沟道区上的存储器单元。 存储单元可各自包括具有隧道绝缘层，形成在存储层上的绝缘层，纳米尺寸电荷存储层以及阻挡绝缘层和侧栅极的存储层。 根据示例实施例，可以实现非易失性存储器件的更大比例的集成，并且存储器件的可靠性可能增加。

公开(公告)号：US20090275177A1

公开(公告)日：2009-11-05

申请号：US12503594

申请日：2009-07-15

申请人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

发明人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L29/1083 ,  H01L29/66787

摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

摘要翻译： 具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并且具有彼此面对的侧壁的一对导电区域。 在导电区域之间的半导体衬底上设置有部分绝缘层。 至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接 到第一个方向。 栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。

公开(公告)号：US20090267137A1

公开(公告)日：2009-10-29

申请号：US12498615

申请日：2009-07-07

申请人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

发明人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

IPC分类号： H01L29/792

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.

摘要翻译： 提供一种制造半导体器件的方法，通过该方法，形成在半导体衬底的单元阵列区域上的单元晶体管采用其中使用间隔物形状的电极形成栅极并且多位操作是 可能使用局部位，并且可以在作为半导体衬底的剩余区域的外围电路区域上形成具有根据晶体管的功能而被优化以满足不同要求的结构的晶体管。 在该方法中，在单元阵列区域上形成单元晶体管。 单元晶体管包括陷波门结构，在陷波栅结构下形成在半导体衬底上的第一沟道区，形成在第一沟道区的两侧的源区和漏区，形成在第一沟道区之间的第一栅极绝缘膜 沟道区域和陷波门结构，以及局部地形成在与第一沟道区和陷波栅结构之间的源极和漏极区相邻的区域上的存储层。 在形成单元晶体管的同时，在外围电路区域上形成有包含至少一个具有与单元晶体管不同的结构的晶体管的多个外围电路晶体管。

公开(公告)号：US07588977B2

公开(公告)日：2009-09-15

申请号：US11452066

申请日：2006-06-13

申请人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

发明人： Sung-dae Suk ,  Sung-young Lee ,  Dong-won Kim ,  Sung-min Kim

IPC分类号： H01L29/768

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/7831

摘要： A method of fabricating a MOSFET provides a plurality of nanowire-shaped channels in a self-aligned manner. According to the method, a first material layer and a semiconductor layer are sequentially formed on a semiconductor substrate. A first mask layer pattern is formed on the semiconductor layer, and recess regions are formed using the first mask layer pattern as an etch mask. A first reduced mask layer pattern is formed, and a filling material layer is formed on the surface of the substrate. A pair of second mask layer patterns are formed, and a first opening is formed. Then, the filling material layer is etched to form a second opening, the exposed first material layer is removed to expose the semiconductor layer, and a gate insulation layer and a gate electrode layer enclosing the exposed semiconductor layer are formed.

摘要翻译： 制造MOSFET的方法以自对准方式提供多个纳米线状通道。 根据该方法，在半导体衬底上依次形成第一材料层和半导体层。 在半导体层上形成第一掩模层图案，并且使用第一掩模层图案作为蚀刻掩模形成凹陷区域。 形成第一缩小的掩模层图案，并且在基板的表面上形成填充材料层。 形成一对第二掩模层图案，形成第一开口。 然后，蚀刻填充材料层以形成第二开口，去除暴露的第一材料层以暴露半导体层，并且形成包围暴露的半导体层的栅极绝缘层和栅极电极层。

公开(公告)号：US20050269629A1

公开(公告)日：2005-12-08

申请号：US11084922

申请日：2005-03-21

申请人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

发明人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/84 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L21/26513 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/78624

摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.

摘要翻译： 翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。 翅片在基底上并沿着和垂直方向横向延伸。 栅电极覆盖翅片的一侧和顶部。 栅绝缘层位于栅电极和鳍之间。 翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。 翅片的源极区域具有与鳍片的漏极区域不同的宽度。

公开(公告)号：US08044451B2

公开(公告)日：2011-10-25

申请号：US12498615

申请日：2009-07-07

申请人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

发明人： Byung-yong Choi ,  Choong-ho Lee ,  Dong-won Kim ,  Dong-gun Park

IPC分类号： H01L29/788

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.

摘要翻译： 提供一种制造半导体器件的方法，通过该方法，形成在半导体衬底的单元阵列区域上的单元晶体管采用其中使用间隔物形状的电极形成栅极并且多位操作是 可能使用局部位，并且可以在作为半导体衬底的剩余区域的外围电路区域上形成具有根据晶体管的功能而被优化以满足不同要求的结构的晶体管。 在该方法中，在单元阵列区域上形成单元晶体管。 单元晶体管包括陷波门结构，在陷波栅结构下形成在半导体衬底上的第一沟道区，形成在第一沟道区的两侧的源区和漏区，形成在第一沟道区之间的第一栅极绝缘膜 沟道区域和陷波门结构，以及局部地形成在与第一沟道区和陷波栅结构之间的源极和漏极区相邻的区域上的存储层。 在形成单元晶体管的同时，在外围电路区域上形成有包含至少一个具有与单元晶体管不同的结构的晶体管的多个外围电路晶体管。

公开(公告)号：US20080283879A1

公开(公告)日：2008-11-20

申请号：US12182593

申请日：2008-07-30

申请人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

发明人： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim

IPC分类号： H01L29/00

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

摘要翻译： 提供具有部分厚度差的栅极介电层的晶体管及其制造方法。 该方法包括形成具有形成在半导体衬底上的较薄厚度的主要部分的栅介质层，以及形成在主体两侧的较厚厚度的侧壁部分。 第一栅极形成为与栅介质层的主要部分重叠，并形成覆盖栅介质层的侧壁部分并覆盖第一栅极的第二栅极层。 蚀刻第二栅极层，从而形成在第一栅极的侧壁上以间隔物形状图案化的第二栅极。 使用第二栅极作为掩模来选择性地蚀刻栅极电介质层的暴露的侧壁部分，从而形成与第二栅极对准的栅极电介质层的图案。 在由第二栅极暴露的半导体衬底的一部分中形成源极/漏极。

公开(公告)号：US20070141796A1

公开(公告)日：2007-06-21

申请号：US11589178

申请日：2006-10-30

申请人： Chang-woo Oh ,  Sung-hwan Kim ,  Dong-gun Park ,  Dong-won Kim

发明人： Chang-woo Oh ,  Sung-hwan Kim ,  Dong-gun Park ,  Dong-won Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/7887

摘要： Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase.

摘要翻译： 示例性实施例涉及半导体存储器件及其形成方法。 其他示例实施例涉及非易失性存储器件及其形成方法。 存储器件可以包括分别形成在形成在衬底上的杂质区域之间的沟道区上的存储器单元。 存储单元可各自包括具有隧道绝缘层，形成在存储层上的绝缘层，纳米尺寸电荷存储层以及阻挡绝缘层和侧栅极的存储层。 根据示例实施例，可以实现非易失性存储器件的更大比例的集成，并且存储器件的可靠性可能增加。