公开(公告)号：US6077738A

公开(公告)日：2000-06-20

申请号：US344398

申请日：1999-06-25

申请人： Yu-Hua Lee ,  Cheng-Ming Wu ,  Tze-Liang Ying

发明人： Yu-Hua Lee ,  Cheng-Ming Wu ,  Tze-Liang Ying

IPC分类号： H01L21/02 ,  H01L21/3105 ,  H01L21/8242 ,  H01L21/20 ,  H01L27/10

CPC分类号： H01L27/10852 ,  H01L21/31053 ,  H01L27/10894 ,  H01L28/91

摘要： A process for obtaining global planarization, or a smooth top surface topography, for an insulator layer overlying a semiconductor chip, with DRAM device structures, featuring crown shaped capacitor structures, and with peripheral, non-DRAM devices, has been developed. The process features the use of a thin silicon nitride shape, used as a hard mask, overlying insulator layers in the peripheral, non-DRAM device region, and used to prevent removal of these underlying insulator layers, during a wet etch procedure which is used to expose the vertical features of crown shaped, storage node structures, in the DRAM device region. The prevention of removal of insulator, located overlying the peripheral, non-DRAM device region, allows a subsequent, planarized, overlying insulator layer, to provide the desired smooth top surface topography for the entire semiconductor chip.

摘要翻译： 已经开发了用于获得覆盖半导体芯片的绝缘体层的全局平坦化或平滑顶表面形貌，具有冠形电容器结构的DRAM器件结构以及外围非DRAM器件的工艺。 该工艺特征在于使用薄的氮化硅形状，用作硬掩模，在外围的非DRAM器件区域中覆盖绝缘体层，并且用于在使用的湿蚀刻过程期间防止这些下面的绝缘体层的去除 以暴露在DRAM器件区域中的冠形存储节点结构的垂直特征。 防止去除位于外围非DRAM器件区域上的绝缘体，允许随后的平坦化的上覆绝缘体层为整个半导体芯片提供所需的平滑顶表面形貌。

公开(公告)号：US06235580B1

公开(公告)日：2001-05-22

申请号：US09467123

申请日：1999-12-20

申请人： Yu-Hua Lee ,  Cheng-Ming Wu ,  Wen-Chuan Chiang

发明人： Yu-Hua Lee ,  Cheng-Ming Wu ,  Wen-Chuan Chiang

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L28/91

摘要： A process for forming crown shaped capacitor structures, for a DRAM device, has been developed. The process features the use of a disposable insulator layer, applied prior to photolithographic and dry etching procedures, used to define the capacitor upper plate structures. The disposable insulator layer alleviates the topography effects presented by crown shaped storage node structures, relaxing the complexity of the patterning of the capacitor upper plate structures.

摘要翻译： 已经开发了用于形成用于DRAM器件的冠形电容器结构的工艺。 该方法的特征在于使用一次性绝缘体层，其在光刻和干蚀刻工艺之前施加，用于限定电容器上板结构。 一次性绝缘体层减轻了冠形存储节点结构呈现的形貌效应，减轻了电容器上板结构图案化的复杂性。

公开(公告)号：US5989784A

公开(公告)日：1999-11-23

申请号：US55463

申请日：1998-04-06

申请人： Yu-Hua Lee ,  Cheng-Ming Wu ,  Chao-Cheng Chen

发明人： Yu-Hua Lee ,  Cheng-Ming Wu ,  Chao-Cheng Chen

IPC分类号： H01L21/768 ,  H01L23/525 ,  G03F7/40 ,  B44C1/22 ,  C03C15/00 ,  C25F3/00

CPC分类号： H01L23/5258 ,  H01L21/76802 ,  H01L2924/0002

摘要： A method of forming an etch stop layer 40 above a fuse 16 in a fuse opening (or window) 92 using a specialized 2 stage etch process. The invention has two important features: First, the etch stop layer 40 is formed from a polysilicon layer (P2 or P4) that is used to fabricate semiconductor devices on a substrate. The etch stop layer 40 is preferably formed of polysilicon layer to is used to from a contact to the substrate 10 (P2) or to form part of a capacitor (P4). Second, a specialized two stage etch process is used where the second stage etches the etch stop layer 40 while simultaneously forming a passivation layer 114 over a metal pad 85. The method comprises: forming fuses 16 over said isolation regions 10 over the fuse area 15; forming a first dielectric layer 30 overlying the fuses 16; forming an etch stop layer 40 over the first dielectric layer 30; forming an insulating layer 43 over the etch stop layer; forming a fuse opening 92 in the insulating layer 43 by etching, in a first etch stage, thorough fuse photoresist openings 90A and stopping the first etch stage on the etch stop layer 40; and etching though the etch stop layer 40 in the fuse opening 92 in a second etch stage.

摘要翻译： 使用专门的2级蚀刻工艺在保险丝开口（或窗口）92中的熔丝16上方形成蚀刻停止层40的方法。 本发明具有两个重要特征：首先，蚀刻停止层40由用于在基板上制造半导体器件的多晶硅层（P2或P4）形成。 蚀刻停止层40优选由多晶硅层形成，用于从接触到衬底10（P2）或形成电容器（P4）的一部分。 第二，使用专门的两级蚀刻工艺，其中第二阶段蚀刻蚀刻停止层40，同时在金属焊盘85上形成钝化层114.该方法包括：在保险丝区域15上方的所述隔离区域10上形成保险丝16 ; 形成覆盖保险丝16的第一电介质层30; 在第一介电层30上形成蚀刻停止层40; 在所述蚀刻停止层上形成绝缘层43; 在绝缘层43中通过在第一蚀刻阶段中蚀刻完整的熔融光致抗蚀剂开口90A并停止蚀刻停止层40上的第一蚀刻阶段来在绝缘层43中形成熔丝开口92; 并且在第二蚀刻阶段通过熔丝开口92中的蚀刻停止层40进行蚀刻。

公开(公告)号：US5985765A

公开(公告)日：1999-11-16

申请号：US75368

申请日：1998-05-11

申请人： Yung-Kuan Hsiao ,  Cheng-Ming Wu ,  Yu-Hua Lee

发明人： Yung-Kuan Hsiao ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/525 ,  H01L21/00

CPC分类号： H01L24/02 ,  H01L23/5256 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14

摘要： A method for reducing bonding pad loss is achieved using a capping layer when contact openings are etched to the bonding pads, while concurrently etching much deeper fuse openings to the substrate. Bonding pads are used on the top surface of integrated circuit semiconductor chips to provide external electrical connections for I/Os and power. And fuses are used in the underlying insulating layers to remove redundant defective circuit elements and thereby repair defective chips. It is desirable (cost effective) to etch the contact openings in the passivation layer to the bonding pads near the top surface on the chip and to concurrently etch the much deeper fuse openings in the thick underlying insulating layers over the fuses. However, because of the difference in etch depth of the two types of openings, the bonding pads composed of Al/Cu are generally overetched causing bond-pad reliability problems. This invention uses a novel process in which a capping layer, having a low etch rate, is formed on the bonding pads to prevent overetching while the fuse openings are etched to the desired depth in the thicker insulating layers.

摘要翻译： 当接触开口被蚀刻到接合焊盘时，使用覆盖层来实现减少焊盘损耗的方法，同时将更深的熔丝开口蚀刻到衬底。 在集成电路半导体芯片的顶面上使用接合焊盘以提供用于I / O和电源的外部电连接。 并且在底层绝缘层中使用熔丝来去除冗余的有缺陷的电路元件，从而修复有缺陷的芯片。 将钝化层中的接触开口蚀刻到芯片顶表面附近的接合焊盘是合乎需要的（成本有效的），同时蚀刻保险丝上较厚的下层绝缘层中更深的熔丝开口。 然而，由于两种类型的开口的蚀刻深度的差异，由Al / Cu组成的焊盘通常是过蚀刻的，导致焊盘可靠性问题。 本发明使用了一种新颖的方法，其中在焊盘上形成具有低蚀刻速率的覆盖层，以防止在较厚绝缘层中将熔丝开口蚀刻到所需深度时的过蚀刻。

公开(公告)号：US6042999A

公开(公告)日：2000-03-28

申请号：US73952

申请日：1998-05-07

申请人： Cheng-Tung Lin ,  Yu-Hua Lee ,  Jenn Ming Huang ,  Cheng-Ming Wu

发明人： Cheng-Tung Lin ,  Yu-Hua Lee ,  Jenn Ming Huang ,  Cheng-Ming Wu

IPC分类号： G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/26

CPC分类号： H01L21/76808 ,  G03F7/0035 ,  H01L21/0276

摘要： A robust dual damascene process is disclosed where the substructure in a substrate is protected from damage caused by multiple etchings required in a damascene process by filling a contact or via hole opening with a protective material prior to the forming of the conductive line opening of the damascene structure having an etch-stop layer separating a lower and an upper dielectric layer. In the first embodiment, the protective material is partially removed from the hole opening reaching the substructure prior to the forming of the upper conductive line opening by etching. In the second embodiment, the protective material in the hole is removed at the same time the upper conductive line opening is formed by etching. In a third embodiment, the disclosed process is applied without the need of an etch-stop layer for the dual damascene process of this invention.

摘要翻译： 公开了一种稳健的双镶嵌工艺，其中通过在形成镶嵌导电线开口之前通过填充具有保护材料的接触或通孔开口来保护衬底中的子结构免受由镶嵌工艺中所需的多次蚀刻所造成的损伤 具有分隔下电介质层和上电介质层的蚀刻停止层的结构。 在第一实施例中，在通过蚀刻形成上导电线开口之前，保护材料部分地从到达底层结构的开孔中去除。 在第二实施例中，在通过蚀刻形成上导电线开口的同时去除孔中的保护材料。 在第三个实施例中，应用所公开的工艺，而不需要用于本发明的双镶嵌工艺的蚀刻停止层。

公开(公告)号：US6015734A

公开(公告)日：2000-01-18

申请号：US148561

申请日：1998-09-04

申请人： Kuo Ching Huang ,  Yu Hua Lee ,  Cheng-Ming Wu

发明人： Kuo Ching Huang ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A new method for forming stacked capacitors for DRAMs having improved yields when the bottom electrode is misaligned to the node contact is achieved. A planar silicon oxide (SiO.sub.2) first insulating layer, a Si.sub.3 N.sub.4 etch-stop layer, and a disposable second insulating layer are deposited. First openings for node contacts are etched in the insulating layers. A polysilicon layer is deposited and etched back to form node contacts in the first openings. The node contacts are recessed in the second insulating layer, but above the etch-stop layer to form node contacts abutting the etch-stop layer. A disposable third SiO.sub.2 layer is deposited. Second openings for bottom electrodes are etched over and to the node contacts. A conformal second polysilicon layer is deposited and chem/mech polished back to form the bottom electrodes in the second openings. The third and second insulating layers are removed by wet etching to the etch-stop layer. When the second openings are misaligned over the node contact openings, the polysilicon plugs abutting the Si.sub.3 N.sub.4 etch-stop layer protect the SiO.sub.2 first insulating layer from being eroded over the devices on the substrate. The capacitors are completed by forming a thin dielectric layer on the bottom electrodes, and forming top electrodes from a patterned third polysilicon layer.

摘要翻译： 实现了当底电极不对准节点接触时，用于形成具有提高的产量的DRAM的叠层电容器的新方法。 沉积平面氧化硅（SiO 2）第一绝缘层，Si 3 N 4蚀刻停止层和一次性第二绝缘层。 在绝缘层中蚀刻用于节点接触的第一开口。 沉积多晶硅层并回蚀刻以在第一开口中形成节点接触。 节点触点凹陷在第二绝缘层中，但在蚀刻停止层之上，以形成邻接蚀刻停止层的节点触点。 沉积一次性第三SiO 2层。 底部电极的第二个开口被蚀刻到节点触点上。 沉积保形的第二多晶硅层，并在第二开口中化学/机械抛光以形成底部电极。 第三绝缘层和第二绝缘层通过湿法蚀刻去除蚀刻停止层。 当第二开口在节点接触开口上不对准时，邻接Si 3 N 4蚀刻停止层的多晶硅栓保护SiO 2第一绝缘层免受衬底上的器件的侵蚀。 通过在底部电极上形成薄的电介质层，并从图案化的第三多晶硅层形成顶部电极来完成电容器。

公开(公告)号：US06307213B1

公开(公告)日：2001-10-23

申请号：US09617427

申请日：2000-07-14

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC分类号： H01L2904

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second poly-silicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.

摘要翻译： 本发明涉及一种用于删除集成电路上的冗余电路元件的新型熔丝结构和方法。 该熔丝结构可用于通过删除存储单元的有缺陷的行来增加RAM芯片的修复产量。 该方法包括在也用于形成互连的图案化导电层中形成熔丝区域。 沉积相对薄的（0.4μm）绝缘层，其跨越衬底具有均匀的厚度。 下一级图案互连形成，其中一部分层在保险丝区域上对齐以用作蚀刻停止层。 例如，导电层可以是RAM芯片上的第一和第二多晶硅层。 然后形成剩余的多层互连件，其具有插入的多个相对较厚的层间电介质层（ILD）层，其可跨越衬底具有累积的厚度变化。 然后在ILD层中选择性地将保险丝窗（开口）蚀刻到蚀刻停止层，并且将蚀刻停止层选择性地在保险丝窗口中蚀刻到保险丝区域上的绝缘层。 该过程允许熔断器结构被建立，而不会导致熔断器损坏。 均匀的厚绝缘层允许可重复且可靠的激光研磨（蒸发）来打开所需的保险丝。

公开(公告)号：US6121073A

公开(公告)日：2000-09-19

申请号：US24479

申请日：1998-02-17

申请人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

发明人： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC分类号： H01L23/525 ,  H01L21/82 ,  H01L27/10

CPC分类号： H01L23/5258 ,  H01L2924/0002

摘要： This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second polysilicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.

摘要翻译： 本发明涉及一种用于删除集成电路上的冗余电路元件的新型熔丝结构和方法。 该熔丝结构可用于通过删除存储单元的有缺陷的行来增加RAM芯片的修复产量。 该方法包括在也用于形成互连的图案化导电层中形成熔丝区域。 沉积相对薄的（0.4μm）绝缘层，其跨越衬底具有均匀的厚度。 下一级图案互连形成，其中一部分层在保险丝区域上对齐以用作蚀刻停止层。 例如，导电层可以是RAM芯片上的第一和第二多晶硅层。 然后形成剩余的多层互连件，其具有插入的多个相对较厚的层间电介质层（ILD）层，其可跨越衬底具有累积的厚度变化。 然后在ILD层中选择性地将保险丝窗（开口）蚀刻到蚀刻停止层，并且将蚀刻停止层选择性地在保险丝窗口中蚀刻到保险丝区域上的绝缘层。 该过程允许熔断器结构被建立，而不会导致熔断器损坏。 均匀的厚绝缘层允许可重复且可靠的激光研磨（蒸发）来打开所需的保险丝。

公开(公告)号：US06103455A

公开(公告)日：2000-08-15

申请号：US73947

申请日：1998-05-07

申请人： Kuo Ching Huang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

发明人： Kuo Ching Huang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC分类号： H01L21/768 ,  G03F7/26

CPC分类号： H01L21/76876 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7688

摘要： A method of forming a deep contact by forming a dielectric layer 20 over a semiconductor structure 10. A main point is that the hard mask 30 is removed after the plug 52 is formed. A hard mask layer 30 is formed over the dielectric layer 20. A contact photoresist layer 36 is formed over the hard mask layer 30. The hard mask layer 30 is etched through the contact photoresist opening 39 to form a contact hard mask opening 41 exposing the dielectric layer 20. The dielectric layer 20 is etched using a high density plasma etch process using the contact photoresist layer 36 and the hard mask layer 30 as an etch mask forming a contact hole 40 in the dielectric layer 20. The contact photoresist layer 36 is removed. A metal layer 50 is formed filling the contact hole 40 and covering over the hard mask layer 30. The metal layer 50 is etched back forming a plug 52 filling the contact hole 40. Now, the hard mask layer 30 is removed. The removal of the hard mask 30 after the metal layer 50 deposition: (a) prevents the contact hole 40 from being contaminated from photoresist and other contamination formed during the hard mask 30 removal steps; and (b) creates a plug 52 that does not have a recess.

摘要翻译： 通过在半导体结构10上形成电介质层20来形成深度接触的方法。主要的一点是在形成插头52之后去除硬掩模30。 在电介质层20上形成硬掩模层30.在硬掩模层30之上形成接触光刻胶层36.硬掩模层30通过接触光致抗蚀剂开口39蚀刻以形成接触硬掩模开口41， 电介质层20.使用接触光致抗蚀剂层36和硬掩模层30作为在电介质层20中形成接触孔40的蚀刻掩模的高密度等离子体蚀刻工艺来蚀刻电介质层20.接触光致抗蚀剂层36是 删除。 形成填充接触孔40并覆盖在硬掩模层30上的金属层50.金属层50被回蚀，形成填充接触孔40的插塞52.现在，去除硬掩模层30。 在金属层50沉积之后去除硬掩模30：（a）防止接触孔40在硬掩模30去除步骤期间被光致抗蚀剂和其它污染物污染; 和（b）产生不具有凹部的插头52。

公开(公告)号：US06187659B1

公开(公告)日：2001-02-13

申请号：US09368861

申请日：1999-08-06

申请人： Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

发明人： Tse-Liang Ying ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC分类号： H01L214763

CPC分类号： H01L27/10855 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897

摘要： A new method is provided to create a gradated dopant concentration in the contact plug of DRAM devices whereby a high dopant concentration is present at the bottom of the plug and a low dopant concentration is present at the top of the plug. Two layers of dielectric are deposited; the upper layer serves as a layer to adjust the dopant concentration in the lower layer. This adjustment is done by Rapid Thermal anneal of both layers of dielectric. After the dopant concentration has been adjusted, the upper layer of dielectric is removed and the upper section of the contact node is formed using lightly doped poly. The high dopant concentration at the bottom of the contact plug results in low contact resistance between the plug and the underlying silicon substrate. A low dopant concentration at the top surface of the contact plug results in low oxidation of the surface of the plug.

摘要翻译： 提供了一种新的方法来在DRAM器件的接触插塞中产生渐变的掺杂剂浓度，由此在插塞的底部存在高的掺杂剂浓度，并且在插头的顶部存在低的掺杂剂浓度。 沉积两层电介质; 上层用作调整下层中的掺杂剂浓度的层。 这种调整是通过两层电介质的快速热退火进行的。 在调整掺杂剂浓度之后，去除电介质的上层，并且使用轻掺杂的多晶形成接触节点的上部。 接触插塞底部的高掺杂剂浓度导致插头和底层硅衬底之间的低接触电阻。 在接触塞顶表面的低掺杂剂浓度导致插塞表面的低氧化。