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    INTERCONNECTION STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR MAKING THE SAME
    4.
    发明申请
    INTERCONNECTION STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR MAKING THE SAME 审中-公开
    半导体集成电路的互连结构及其制造方法

    公开(公告)号：US20100314765A1

    公开(公告)日：2010-12-16

    申请号：US12485909

    申请日：2009-06-16

    Applicant: Wen-Ping Liang ,  Yu-Shan Chiu ,  Kuo-Hui Su

    Inventor： Wen-Ping Liang ,  Yu-Shan Chiu ,  Kuo-Hui Su

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/53214 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnection structure includes a lower layer metal wire in a first inter-metal dielectric layer on a substrate; a second inter-metal dielectric layer on the first inter-metal dielectric layer and covering the lower layer metal wire; an upper layer metal wire on the second inter-metal dielectric layer; and a via interconnection structure in the second inter-metal dielectric layer for interconnecting the upper layer metal wire with the lower layer metal wire, wherein the via interconnection structure comprises a tungsten stud on the lower layer metal wire, and an aluminum plug stacked on the tungsten stud.

    Abstract translation: 互连结构包括在基板上的第一金属间介电层中的下层金属线; 在所述第一金属间电介质层上的第二金属间介电层，并覆盖所述下层金属线; 在第二金属间介电层上的上层金属线; 以及用于将上层金属线与下层金属线互连的第二金属间介质层中的通孔互连结构，其中通孔互连结构包括在下层金属线上的钨螺柱和堆叠在下层金属线上的铝塞 钨螺柱

    METHOD OF FORMING CONDUCTIVE PATTERN
    7.
    发明申请
    METHOD OF FORMING CONDUCTIVE PATTERN 有权
    形成导电图案的方法

    公开(公告)号：US20130052820A1

    公开(公告)日：2013-02-28

    申请号：US13214244

    申请日：2011-08-22

    Applicant: Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

    Inventor： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

    IPC: H01L21/28

    CPC classification number: H01L21/321 ,  H01L21/76856 ,  H01L21/76861 ,  H01L21/76876 ,  H01L21/76885

    Abstract: A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other.

    Abstract translation: 提供形成导电图案的方法。 在底层上形成接种层。 通过使用能量射线，对接种层的表面的一部分进行照射处理。 因此，接种层包括多个照射区域和多个未照射区域。 对接种层的照射区域进行转化处理。 进行选择性生长处理，以在接种层的每个未照射区域上形成导电图案。 去除接种层的照射区域，使得导电图案彼此绝缘。

    Method for fabricating semiconductor device having stacked-gate structure
    8.
    发明授权
    Method for fabricating semiconductor device having stacked-gate structure 有权
    具有层叠栅结构的半导体器件的制造方法

    公开(公告)号：US07022603B2

    公开(公告)日：2006-04-04

    申请号：US10683612

    申请日：2003-10-10

    Applicant: Tzu-En Ho ,  Chih-Hao Chang ,  Chang-Rong Wu ,  Kuo-Hui Su

    Inventor： Tzu-En Ho ,  Chih-Hao Chang ,  Chang-Rong Wu ,  Kuo-Hui Su

    IPC: H01L21/44

    CPC classification number: H01L21/28052 ,  H01L29/4933

    Abstract: A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

    Abstract translation: 一种半导体制造方法，该半导体器件具有堆叠栅极结构。 通过介电层与衬底绝缘的衬底上形成多晶硅层。 在多晶硅层上形成金属闪光层，然后在钛层上形成氮化钨层。 使用氮气和氢气对氮化钨层进行退火。 依次形成覆盖氮化钨层的钨层和覆盖层。

    SEMICONDUCTOR DEVICE HAVING VERTICAL GATES AND FABRICATION THEREOF
    9.
    发明申请
    SEMICONDUCTOR DEVICE HAVING VERTICAL GATES AND FABRICATION THEREOF 有权
    具有垂直门和其制造的半导体器件

    公开(公告)号：US20140021535A1

    公开(公告)日：2014-01-23

    申请号：US13555640

    申请日：2012-07-23

    Applicant: Wen-Ping Liang ,  Chiang-Hung Lin ,  Kuo-Hui Su

    Inventor： Wen-Ping Liang ,  Chiang-Hung Lin ,  Kuo-Hui Su

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/4236 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66621 ,  H01L29/78

    Abstract: A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer.

    Abstract translation: 公开了一种用于形成具有垂直栅极的半导体器件的方法，包括提供衬底，在衬底中形成凹槽，在凹槽的侧壁和底部上形成栅极电介质层，在凹部中形成粘附层， 所述栅介电层，其中所述粘附层是金属硅化物氮化物层，并且在所述凹部中和所述粘合层上形成栅极层。

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