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    Semiconductor package
    1.
    发明授权
    Semiconductor package 有权
    半导体封装

    公开(公告)号：US06509636B1

    公开(公告)日：2003-01-21

    申请号：US10039251

    申请日：2002-01-02

    申请人： Yueh-Ying Tsai ,  Chin-Yuan Hung ,  Chang-Fu Chen

    发明人： Yueh-Ying Tsai ,  Chin-Yuan Hung ,  Chang-Fu Chen

    IPC分类号： H01L2302

    CPC分类号： H01L23/10 ,  H01L27/14618 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/16315 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A photosensitive semiconductor package with a lid is proposed, in which a chip carrier is formed with an encapsulant thereon, and the encapsulant is formed with a cavity for exposing a semiconductor chip mounted on the chip carrier. A top of the encapsulant is structured with a groove and at least a beveled portion that descends toward the groove and is associated with the groove. When a lid is attached onto the encapsulant by using an adhesive, the groove can temporarily retain excess adhesive with its flow being directed toward the groove by the beveled portion, so that undersirable adhesive loss and adhesive flash can both be prevented from occurrence, allowing the appearance of the semiconductor package to be well maintained.

    摘要翻译： 提出了具有盖的光敏半导体封装，其中在其上形成有密封剂的芯片载体，并且密封剂形成有用于暴露安装在芯片载体上的半导体芯片的空腔。 密封剂的顶部被构造成具有凹槽和至少一个倾斜的部分，该斜面部分朝着凹槽下降并与凹槽相关联。 当通过使用粘合剂将盖子附着到密封剂上时，槽可以暂时保留多余的粘合剂，其流动通过倾斜部分指向凹槽，使得可以防止不希望的粘合剂损失和粘合剂闪光发生，从而允许 半导体封装的外观要保持良好。

    Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package
    3.
    发明授权
    Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package 有权
    引线框，带有裸片焊盘上镀银区域的阵列，用于裸焊盘半导体封装

    公开(公告)号：US06396129B1

    公开(公告)日：2002-05-28

    申请号：US09800361

    申请日：2001-03-05

    申请人： Chin-Yuan Hung ,  Chang-Fu Chen ,  Fu-Di Tang

    发明人： Chin-Yuan Hung ,  Chang-Fu Chen ,  Fu-Di Tang

    IPC分类号： H01L23495

    CPC分类号： H01L24/32 ,  H01L23/49503 ,  H01L23/49513 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

    摘要： A leadframe with a dot array of silver-plated regions on die pad is proposed, which is designed specifically for use in the construction of an exposed-pad type of semiconductor package. The proposed leadframe is characterized by that the front side of the die pad is partitioned into a centrally-located die-mounting area and a peripherally-located ground-wire bonding area; and wherein the die-mounting area is selectively silver-plated to form a dot array of silver-plated regions, while the peripheral area of the die pad is entirely silver-plated to form a silver-plated peripheral area. In addition, the die-mounting area of the die pad can be further formed with a plurality of dimples for the purpose of increasing the contact area between the die pad and a silver-epoxy layer that is to be pasted over the die-mounting area for use to adhere a semiconductor chip to the die pad. Owing to the provision of the dot array of silver-plated regions within the die-mounting area, it allows a better electrical coupling between the die pad and the inactive surface of the semiconductor chip than the conventional ring plating scheme so that the packaged semiconductor chip can have a better grounding effect, and also allows the silver-epoxy layer to be better adhered to the die pad than the conventional spotted plating scheme to prevent delamination.

    摘要翻译： 提出了一种引线框架，其具有在芯片焊盘上的镀银区域的阵列阵列，其被专门设计用于暴露焊盘型半导体封装的构造。 所提出的引线框架的特征在于，芯片焊盘的前侧被分隔成中心定位的管芯安装区域和位于外围的接地引线接合区域; 并且其中，所述管芯安装区域被选择性地镀银以形成镀银区域的点阵列，同时所述管​​芯焊盘的周边区域被完全镀银以形成镀银周边区域。 此外，芯片焊盘的管芯安装区域可以进一步形成有多个凹坑，目的是增加管芯焊盘和待粘贴在管芯安装区域上的银环氧树脂层之间的接触面积 用于将半导体芯片粘附到管芯焊盘。 由于在芯片安装区域内设置镀银区域的点阵列，所以允许芯片焊盘和半导体芯片的非活性表面之间的电气耦合比传统的环形电镀方案更好地电连接，使得封装的半导体芯片 可以具有更好的接地效果，并且还允许银环氧树脂层比常规的点电镀方案更好地粘附到芯片焊盘，以防止分层。

    Package structure having tapering support bars and leads
    4.
    发明授权
    Package structure having tapering support bars and leads 有权
    包装结构具有锥形支撑杆和导线

    公开(公告)号：US06696749B1

    公开(公告)日：2004-02-24

    申请号：US09669005

    申请日：2000-09-25

    申请人： Chin-Yuan Hung ,  Lien-Chen Chiang

    发明人： Chin-Yuan Hung ,  Lien-Chen Chiang

    IPC分类号： H01L23495

    CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A package structure having tapering support bars and leads. The package structure has at least a lead frame, a die, a plurality of conductive wires and an encapsulating plastic body. The lead frame has a first surface and has at least a package unit. The package unit has a die pad, a plurality of leads and a plurality of support bars. The die pad is positioned in the middle. The leads and support bars are distributed around the periphery of the package unit. In addition, the width of the leads and support bars decreases gradually from a location close to the die pad towards the peripheral region. The leads and support bars have a rectangular or trapezoidal cross-section. A die is bonded on the surface of the die pad and the die is electrically connected to the leads on the lead frame via a plurality of conductive wires. Plastic material such as epoxy resin encloses the die, the conductive wires and the first surface of the lead frame.

    摘要翻译： 具有锥形支撑杆和引线的封装结构。 封装结构至少具有引线框架，管芯，多个导电线和封装塑料体。 引线框架具有第一表面并且至少具有封装单元。 封装单元具有管芯焊盘，多个引线和多个支撑杆。 芯片垫位于中间。 引线和支撑杆分布在封装单元的周围。 此外，引线和支撑杆的宽度从靠近管芯焊盘的位置朝向周边区域逐渐减小。 引线和支撑杆具有矩形或梯形横截面。 芯片焊接在芯片焊盘的表面上，芯片通过多根导线与引线框架上的引线电连接。 诸如环氧树脂的塑料材料封装模具，导线和引线框架的第一表面。

    Multi-chip semiconductor package
    5.
    发明授权
    Multi-chip semiconductor package 失效
    多芯片半导体封装

    公开(公告)号：US06495908B2

    公开(公告)日：2002-12-17

    申请号：US09973359

    申请日：2001-10-09

    申请人： Cheng-Hsung Yang ,  Chin-Yuan Hung ,  Jian-Xheng Liu

    发明人： Cheng-Hsung Yang ,  Chin-Yuan Hung ,  Jian-Xheng Liu

    IPC分类号： H01L23495

    CPC分类号： H01L23/4951 ,  H01L21/565 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A multi-hip semiconductor package is proposed, in which a first chip and a second chip are mounted on opposing surfaces of a lead frame in a staggered manner. This staggered arrangement assures the die bonding quality for firmly disposing the second chip in the semiconductor package without being detrimental affected by the first chip. Moreover, as both opposing surfaces of the lead frame have chips mounted thereon, a mold flow of a molding resin used in a molding process can be balanced, so that turbulence the mold flow is decreased, and void formation can be avoided. In addition, the semiconductor package can incorporate a third chip in a stacked manner with respect to the first or second chip. This therefore further improves the functionality and performance of the semiconductor package.

    摘要翻译： 提出了一种多髋半导体封装，其中第一芯片和第二芯片以交错方式安装在引线框架的相对表面上。 这种交错布置确保了芯片接合质量，以将第二芯片牢固地布置在半导体封装中，而不会受到第一芯片的不利影响。 此外，由于引线框架的两个相对表面都具有安装在其上的芯片，因此可以平衡在模制过程中使用的模制树脂的模具流动，从而减少模具流动的紊流，并且可以避免形成空隙。 此外，半导体封装可以相对于第一或第二芯片以堆叠的方式并入第三芯片。 因此，这进一步提高了半导体封装的功能和性能。

    Quad flat non-leaded package structure for housing CMOS sensor
    7.
    发明授权
    Quad flat non-leaded package structure for housing CMOS sensor 有权
    用于外壳CMOS传感器的四边形无铅封装结构

    公开(公告)号：US06476469B2

    公开(公告)日：2002-11-05

    申请号：US09842040

    申请日：2001-04-25

    申请人： Chin-Yuan Hung ,  Lien-Chen Chiang ,  Cheng-Shiu Hsiao

    发明人： Chin-Yuan Hung ,  Lien-Chen Chiang ,  Cheng-Shiu Hsiao

    IPC分类号： H01L23495

    CPC分类号： H01L23/49861 ,  H01L21/565 ,  H01L23/49503 ,  H01L24/45 ,  H01L24/48 ,  H01L27/14618 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2224/05599

    摘要： A quad flat non-leaded package structure for housing a sensor. The package includes a die pad, a plurality of leads, a die, a plurality of bonding wires, a packaging plastic body and a lid cover. A plurality of supporters are formed near the edges on the backside of the die pad. The plurality of leads is positioned at a well-defined distance away from the four sides of the die pad. The packaging plastic body is formed on the upper surface near the peripheral section of the leads. The space between the die pad and the leads is filled by the packaging plastic material but the bottom section of the leads and the bottom section of the supporters on the backside of the die pad are exposed. The die is attached to the upper surface of the die pad and is electrically connected to the leads using the bonding wires. The lid cover is placed over the packaging plastic body.

    摘要翻译： 用于容纳传感器的四边形无铅封装结构。 封装包括管芯焊盘，多个引线，管芯，多个接合线，封装塑料体和盖罩。 在芯片的背面的边缘附近形成多个支撑体。 多个引线位于远离模具垫的四个侧面的明确的距离处。 包装塑料体形成在引线的周边部分附近的上表面上。 芯片焊盘和引线之间的空间由包装塑料材料填充，但引线的底部和裸片垫背面的支撑体的底部部分露出。 模具附接到管芯焊盘的上表面，并且使用接合线电连接到引线。 盖盖放置在包装塑料体上。