公开(公告)号：US20120200549A1

公开(公告)日：2012-08-09

申请号：US13395518

申请日：2010-04-23

申请人： Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

发明人： Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3659 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2320/0219 ,  G09G2330/022

摘要： Provided is a display device which can prevent screen noise caused such that a potential of a common electrode is reversed after a memory mode enters from a refresh period to an entire write-in period, and a method for driving the display device. The memory mode includes (i) an entire write-in period in which a potential of the common electrode (COM) is fixed and the display data is written into all the memory circuits (node (PIX)) in each row and (ii) a refresh period in which the display data which has been written during the entire write-in period is refreshed at least once while the common electrode (COM) is driven. In the memory mode, the potential of the common electrode during the entire write-in period being a potential which the common electrode having been driven had at the end of a refresh period preceding the entire write-in period.

摘要翻译： 提供一种显示装置，其可以防止在从刷新周期进入整个写入周期之后引起公共电极的电位反转的屏幕噪声，以及用于驱动显示装置的方法。 存储模式包括：（i）公共电极（COM）的电位固定并将显示数据写入到每行的所有存储电路（节点（PIX））中的整个写入周期，以及（ii） 在驱动公共电极（COM）的过程中至少刷新一次整个写入周期期间已写入的显示数据的刷新周期。 在存储模式中，公共电极在整个写入周期期间的电位是已经被驱动的公共电极在整个写入周期之前的刷新周期结束时的电位。

公开(公告)号：US20120169753A1

公开(公告)日：2012-07-05

申请号：US13496027

申请日：2010-04-23

申请人： Yuhichiroh Murakami ,  Shige Furuta ,  Yasushi Sasaki ,  Seijirou Gyouten ,  Shuji Nishi

发明人： Yuhichiroh Murakami ,  Shige Furuta ,  Yasushi Sasaki ,  Seijirou Gyouten ,  Shuji Nishi

IPC分类号： G09G5/36 ,  G11C7/00 ,  G11C5/06

CPC分类号： G09G3/3659 ,  G09G2300/0417 ,  G09G2300/0823 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2300/088 ,  G09G2330/022 ,  G11C11/405

摘要： A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.

摘要翻译： 提供了一种存储器件，其包括一个存储器电路，即使在转印部件中使用的转印元件中出现泄漏电流，允许进行刷新操作的电路适当地执行电路的原始操作。 存储单元包括开关电路，第一保持部分，转移部分，第二保持部分，第一控制部分和电压源，并且第一控制部分被控制为处于（i） 第一控制部分执行第一操作，其中第一控制部分处于活动状态或非活动状态，以及（ii）第一控制部分执行第二操作的状态。

公开(公告)号：US20120176393A1

公开(公告)日：2012-07-12

申请号：US13395977

申请日：2010-04-23

申请人： Hiroyuki Ohkawa ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

发明人： Hiroyuki Ohkawa ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

IPC分类号： G09G5/36 ,  G11C5/02

CPC分类号： G09G3/3648 ,  G09G2300/0852 ,  G09G2300/0857 ,  G09G2310/06 ,  G09G2320/0219

摘要： Provided is a memory device that allows an amount of leakage into a first retaining section to which a binary logic level is written to be balanced between different circuit states. A predetermined period is set in which in a state where a first control section turns off an output element, (i) a first retaining section and a second retaining section retain an identical binary logic level, (ii) an electric potential of a voltage supply is set to one of a first electric potential level and a second electric potential level, (iii) the other one of the first electric potential level and the second electric potential level is supplied from a column driver to a fourth wire, and (iv) subsequently the fourth wire is shifted to a floating state.

摘要翻译： 提供了一种存储器件，其允许向写入二进制逻辑电平的第一保持部分的泄漏量在不同的电路状态之间平衡。 设定规定期间，其中在第一控制部分关闭输出元件的状态下，（i）第一保持部分和第二保持部分保持相同的二进制逻辑电平，（ii）电压源的电位 被设置为第一电位电平和第二电位电平之一，（iii）第一电位电平和第二电位电平中的另一个从列驱动器提供给第四线，以及（iv） 随后第四根线移动到浮动状态。

公开(公告)号：US20120169751A1

公开(公告)日：2012-07-05

申请号：US13395681

申请日：2010-05-18

申请人： Etsuo Yamamoto ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

发明人： Etsuo Yamamoto ,  Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

IPC分类号： G06F3/038 ,  G09G5/39

CPC分类号： G09G3/3648 ,  G02F1/13624 ,  G09G3/3614 ,  G09G2300/0857 ,  G09G2310/08 ,  G09G2320/0219 ,  G09G2330/021

摘要： In an active matrix display apparatus including: pixels provided in a matrix pattern, the pixels each including a memory circuit which retains data while refreshing the data, a data signal electric potential which is supplied from a source line in a period t1 and written to a node which is connected to a liquid capacitor is higher than a data electric potential of the node, the data electric potential being obtained in a period t14 after a refresh operation of the memory circuit.

摘要翻译： 在一种有源矩阵显示装置中，包括以矩阵模式提供的像素，每个像素包括一个在刷新数据的同时保留数据的存储电路，在时间段t1内从源极线提供的数据信号电位被写入到 连接到液体电容器的节点高于节点的数据电位，在存储器电路的刷新操作之后的周期t14中获得数据电位。

公开(公告)号：US20120169750A1

公开(公告)日：2012-07-05

申请号：US13394606

申请日：2010-04-23

申请人： Yuhichiroh Murakami ,  Yasushi Sasaki ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

发明人： Yuhichiroh Murakami ,  Yasushi Sasaki ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

IPC分类号： G09G5/39

CPC分类号： G09G3/3659 ,  G02F1/13624 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2330/022

摘要： Provided are a memory-type display device capable of improving image quality during a normal mode and a method for driving such a display device. Each memory circuit (MR1) includes: a node (PIX) (pixel electrode); a node (MRY) (memory electrode); a switch circuit (SW1); a first data-retention section (DS1) composed of a capacitor (Ca1); a data transfer section (TS1) composed of a transistor (N2); a second data-retention section (DS2) composed of a capacitor (Cb1); and a refresh output control section (RS1) including a transistor (N4). During the normal mode, and the capacitor (Ca1) and the capacitor (Cb1) are both used as auxiliary capacitors with the transistor (N2) in a conductive state and the transistor (N4) in a cutoff state.

摘要翻译： 提供了能够在正常模式下提高图像质量的记忆型显示装置以及用于驱动这种显示装置的方法。 每个存储器电路（MR1）包括：节点（PIX）（像素电极）; 节点（MRY）（记忆电极）; 开关电路（SW1）; 由电容器（Ca1）组成的第一数据保持部（DS1）; 由晶体管（N2）构成的数据传送部（TS1）; 由电容器（Cb1）构成的第二数据保持部（DS2）; 以及包括晶体管（N4）的刷新输出控制部分（RS1）。 在正常模式期间，电容器（Ca1）和电容器（Cb1）都用作具有导通状态的晶体管（N2）和晶体管（N4）处于截止状态的辅助电容器。

公开(公告)号：US20120169690A1

公开(公告)日：2012-07-05

申请号：US13395697

申请日：2010-04-23

申请人： Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

发明人： Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3607 ,  G09G3/3614 ,  G09G3/3618 ,  G09G3/3655 ,  G09G3/3659 ,  G09G2300/0814 ,  G09G2300/0823 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2320/0219 ,  G09G2330/021 ,  G09G2330/022

摘要： Provided are a display device capable of preventing image noise arising from changes in potential of a common electrode and auxiliary capacitor lines at the time of a switch between a normal mode and a memory mode and a method for driving such a display device. In a case where it is necessary to cause the common electrode and the auxiliary capacitor lines to change in potential along with a switch between the normal mode and the memory mode, the change in potential is made while electrically connecting a node of each memory circuit to a corresponding source line with the corresponding source line having its potential fixed and with the memory circuit having its a switch circuit in a conductive state.

摘要翻译： 提供了能够防止在正常模式和存储模式之间的切换时由公共电极和辅助电容器线的电位变化引起的图像噪声的显示装置以及用于驱动这种显示装置的方法。 在需要使公共电极和辅助电容线与正常模式和存储模式之间的切换一起改变电位的情况下，在将每个存储器电路的节点电连接到 对应的源极线，其相应的源极线具有其电位固定，并且存储电路具有其导通状态的开关电路。

公开(公告)号：US08866719B2

公开(公告)日：2014-10-21

申请号：US13395549

申请日：2010-05-18

申请人： Shuji Nishi ,  Yuhichiroh Murakami ,  Shige Furuta ,  Yasushi Sasaki ,  Seijirou Gyouten

发明人： Shuji Nishi ,  Yuhichiroh Murakami ,  Shige Furuta ,  Yasushi Sasaki ,  Seijirou Gyouten

IPC分类号： G09G3/36 ,  H01L27/108 ,  G11C11/406 ,  H01L27/12

CPC分类号： H01L27/108 ,  G09G3/3614 ,  G09G3/3618 ,  G09G3/3648 ,  G09G3/3659 ,  G09G2300/0823 ,  G09G2300/0852 ,  G09G2330/021 ,  G11C11/406 ,  G11C2211/4067 ,  H01L27/12

摘要： A transistor (N1) has a gate terminal connected to a word line (Xi(1)) and a first conduction terminal connected to a bit line (Yj). A transistor (N2) has a gate terminal connected to the word line (Xi(2)) and a first conduction terminal connected to a node (PIX). A transistor (N3) has a gate terminal connected to a node (MRY) and a first conduction terminal connected to the word line (Xi(2)). A transistor (N4) has a gate terminal connected to the word line (Xi(3)), a first conduction terminal connected to a second conduction terminal of the transistor (N3), and a second conduction terminal connected to the node (PIX). Capacitors (Ca1), (Cb1), (Cap1) are formed between the node (PIX) and a reference electric potential wire (RL1), between the node (MRY) and the reference electric potential wire (RL1), and between the first conduction terminal of the transistor (N3) and the node (MRY), respectively.

摘要翻译： 晶体管（N1）具有连接到字线（Xi（1））的栅极端子和连接到位线（Yj）的第一导电端子。 晶体管（N2）具有连接到字线（Xi（2））的栅极端子和连接到节点（PIX）的第一导电端子。 晶体管（N3）具有连接到节点（MRY）的栅极端子和连接到字线（Xi（2））的第一导电端子。 晶体管（N4）具有连接到字线（Xi（3））的栅极端子，连接到晶体管（N3）的第二导通端子的第一导电端子和连接到节点（PIX）的第二导电端子， 。 在节点（MRY）和参考电位线（RL1）之间以及在第一（VI））之间的节点（PIX）和参考电位线（RL1）之间形成电容器（Ca1），（Cb1） 晶体管（N3）和节点（MRY）的导通端子。

公开(公告)号：US08775842B2

公开(公告)日：2014-07-08

申请号：US13395739

申请日：2010-05-18

申请人： Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

发明人： Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

IPC分类号： G06F1/32

CPC分类号： G09G3/3659 ,  G09G2300/0857 ,  G09G2310/08 ,  G09G2320/0219 ,  G09G2330/022

摘要： A memory device can perform a first operation mode in which a discrete level is supplied to cause the memory cell to retain a logical level, and prevent unnecessary power consumption due to an operation of a power source which is unnecessary in the first operation mode. The memory device includes: a first power source for supplying a first potential level; a second power source for supplying a second potential level, a third power source for supplying a potential higher than a highest potential of discrete levels; and a fourth power source for supplying a potential lower than a lowest potential of the discrete levels, the first and second potential levels being used to supply the discrete levels, when the first operation is carried out, VDD, VSS, and GVDD being caused to be in operation and the fourth power source being stopped from being in operation.

摘要翻译： 存储器件可以执行其中提供离散电平以使存储器单元保持逻辑电平的第一操作模式，并且防止由于在第一操作模式中不必要的电源的操作引起的不必要的功耗。 存储器件包括：用于提供第一电位电平的第一电源; 用于提供第二电位电平的第二电源，用于提供高于离散电平的最高电位的电位的第三电源; 以及用于提供低于所述离散电平的最低电位的电位的第四电源，所述第一和第二电位电平用于提供所述离散电平，当执行所述第一操作时，引起VDD，VSS和GVDD 运行中，第四个电源停止工作。

公开(公告)号：US20120179923A1

公开(公告)日：2012-07-12

申请号：US13395739

申请日：2010-03-18

申请人： Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

发明人： Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shige Furuta ,  Seijirou Gyouten ,  Shuji Nishi

IPC分类号： G06F1/26

CPC分类号： G09G3/3659 ,  G09G2300/0857 ,  G09G2310/08 ,  G09G2320/0219 ,  G09G2330/022

摘要： A memory device can perform a first operation mode in which a discrete level is supplied to cause the memory cell to retain a logical level, and prevent unnecessary power consumption due to an operation of a power source which is unnecessary in the first operation mode. The memory device includes: a first power source (VDD) for supplying a first potential level; a second power source (VSS) for supplying a second potential level, a third power source (GVDD) for supplying a potential higher than a highest potential of discrete levels; and a fourth power source for supplying a potential lower than a lowest potential of the discrete levels, the first and second potential levels being used to supply the discrete levels, when the first operation is carried out, VDD, VSS, and GVDD being caused to be in operation and the fourth power source being stopped from being in operation.

摘要翻译： 存储器件可以执行其中提供离散电平以使存储器单元保持逻辑电平的第一操作模式，并且防止由于在第一操作模式中不必要的电源的操作引起的不必要的功耗。 存储器件包括：用于提供第一电位电平的第一电源（VDD）; 用于提供第二电位电平的第二电源（VSS）;用于提供高于离散电平的最高电位的电位的第三电源（GVDD）; 以及用于提供低于所述离散电平的最低电位的电位的第四电源，所述第一和第二电位电平用于提供所述离散电平，当执行所述第一操作时，引起VDD，VSS和GVDD 运行中，第四个电源停止工作。

公开(公告)号：US20120176388A1

公开(公告)日：2012-07-12

申请号：US13395536

申请日：2010-05-26

申请人： Makoto Yokoyama ,  Shige Furuta ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten ,  Shuji Nishi

发明人： Makoto Yokoyama ,  Shige Furuta ,  Yuhichiroh Murakami ,  Yasushi Sasaki ,  Seijirou Gyouten ,  Shuji Nishi

IPC分类号： G09G5/39

CPC分类号： G09G3/3648 ,  G02F1/13624 ,  G09G2300/043 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0876 ,  G09G2310/063 ,  G09G2310/08 ,  G09G2320/0219 ,  G09G2320/0247 ,  G09G2340/0428

摘要： In a memory liquid crystal display device, a potential of a storage capacitor line signal (CS) supplied to the CS lines (CSL(i)) are once decreased (ΔVcs) while the gate lines (GL(i)) are made simultaneously active (period t4, period t10) in the data holding period (T2), and the potential of the storage capacitor line signal (CS) is made back to its original potential while the gate lines (GL(i)) are made simultaneously inactive and the refresh output control lines (RC(i)) are made active (period t5, period t11). This reduces flicker, thereby allowing for improvement in display quality of the memory liquid crystal display device.

摘要翻译： 在存储器液晶显示装置中，提供给CS线（CSL（i））的辅助电容配线信号（CS）的电位在制作栅极线（GL（i））时一度减小（＆Dgr; Vcs） 数据保持期间（T2）中同时有效（周期t4，期间t10），并且保持电容配线信号（CS）的电位恢复到原来的电位，而同时进行栅极线（GL（i）） 并且刷新输出控制线（RC（i））被激活（时段t5，周期t11）。 这减少了闪烁，从而可以提高存储器液晶显示装置的显示质量。