公开(公告)号：US20100295047A1

公开(公告)日：2010-11-25

申请号：US12864480

申请日：2009-01-23

申请人： Masao Moriguchi ,  Yuichi Saito ,  Akihiko Kohno

发明人： Masao Moriguchi ,  Yuichi Saito ,  Akihiko Kohno

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/78618 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78696

摘要： To provide a semiconductor device which achieves a high ON current and a low OFF current at the same time, and a fabrication method thereof.A semiconductor device of the present invention includes a glass substrate 1, an island-shaped semiconductor layer 4 which includes a first region 4c, a second region 4a, and a third region 4c, a source region 5a and a drain region 5b, a source electrode 6a, a drain electrode 6b, and a gate electrode 2 for controlling the conductivity of the first region 4c. The upper surface of the first region 4c is closer to the glass substrate 1 than the upper surfaces of ends of the second region 4a and the third region 4b adjacent to the first region 4c are. The distances between the upper surfaces of the ends of the second region 4a and the third region 4b and the upper surface of the first region 4c along the thickness direction of the semiconductor layer 4 are each independently not less than one time and not more than seven times the thickness of the first region 4b.

摘要翻译： 提供同时实现高导通电流和低关断电流的半导体器件及其制造方法。 本发明的半导体器件包括玻璃基板1，岛状半导体层4，其包括第一区域4c，第二区域4a和第三区域4c，源极区域5a和漏极区域5b，源极 电极6a，漏电极6b和用于控制第一区域4c的导电性的栅电极2。 第一区域4c的上表面比第二区域4a的端部的上表面和邻近第一区域4c的第三区域4b更靠近玻璃基板1。 第二区域4a和第三区域4b的端部的上表面与第一区域4c的上表面之间的距离沿着半导体层4的厚度方向分别独立地不小于一个时间并且不超过七个 乘以第一区域4b的厚度。

公开(公告)号：US08378348B2

公开(公告)日：2013-02-19

申请号：US12864461

申请日：2009-01-08

申请人： Yuichi Saito ,  Masao Moriguchi ,  Akihiko Kohno

发明人： Yuichi Saito ,  Masao Moriguchi ,  Akihiko Kohno

IPC分类号： H01L31/00

CPC分类号： H01L29/78669 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78678

摘要： A semiconductor device 101 includes: a substrate 1; an active layer 4 provided on the substrate 1 and including a channel region 4c, and a first region 4a and a second region 4b that are respectively located on opposite sides of the channel region 4c; first and second contact layers 6a and 6b respectively in contact with the first and second regions 4a and 4b of the active layer 4; a first electrode 7 electrically coupled to the first region 4a via the first contact layer 6a; a second electrode 8 electrically coupled to the second region 4b via the second contact layer 6b; and a gate electrode 2 provided such that a gate insulating layer 3 is interposed between the gate electrode 2 and the active layer 4, the gate electrode 2 being configured to control a conductivity of the channel region 4c. The active layer 4 contains silicon. The semiconductor device further includes an oxygen-containing silicon layer 5 between the active layer 4 and the first and second contact layers 6a, 6b. The layer 5 contains oxygen at a concentration higher than the active layer 4 and the first and second contact layers 6a, 6b.

摘要翻译： 半导体器件101包括：衬底1; 设置在基板1上并且包括沟道区域4c的有源层4和分别位于沟道区域4c的相对侧上的第一区域4a和第二区域4b; 分别与有源层4的第一和第二区域4a和4b接触的第一和第二接触层6a和6b; 经由第一接触层6a电耦合到第一区域4a的第一电极7; 经由第二接触层6b电耦合到第二区域4b的第二电极8; 栅极电极2被设置为使得栅极绝缘层3插入在栅电极2和有源层4之间，栅电极2被配置为控制沟道区域4c的导电性。 有源层4含有硅。 半导体器件还包括有源层4和第一和第二接触层6a，6b之间的含氧硅层5。 层5含有浓度高于有源层4和第一和第二接触层6a，6b的氧。

公开(公告)号：US20120104403A1

公开(公告)日：2012-05-03

申请号：US13381282

申请日：2010-02-22

申请人： Akihiko Kohno ,  Masao Moriguchi ,  Yuhichi Saitoh

发明人： Akihiko Kohno ,  Masao Moriguchi ,  Yuhichi Saitoh

IPC分类号： H01L29/786 ,  H01L29/04 ,  H01L21/336

CPC分类号： H01L21/0217 ,  H01L21/022 ,  H01L29/04 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78678

摘要： An object of the present invention is to provide a thin film transistor having a gate insulating film for suppressing a shift amount of a threshold voltage generated by use under a high temperature environment. In a thin film transistor having a channel layer made of microcrystalline silicon, a gate insulating film 140 is a film obtained by laminating a first silicon nitride film 141 having a nitrogen concentration of 6×1021 atoms/cc or less and a second silicon nitride film 142 having a nitrogen concentration higher than 6×1021 atoms/cc. Therefore, the second silicon nitride film 142 increases the blocking effect against mobile ions entering from a glass substrate 20 to make the mobile ions less likely to be stored in an interface with a channel layer 50. The first silicon nitride film 141 increases the dielectric breakdown voltage of the gate insulating film 140.

摘要翻译： 本发明的目的是提供一种薄膜晶体管，其具有用于抑制在高温环境下使用产生的阈值电压的偏移量的栅极绝缘膜。 在具有由微晶硅制成的沟道层的薄膜晶体管中，栅极绝缘膜140是通过层叠氮浓度为6×1021原子/ cc以下的第一氮化硅膜141和第二氮化硅膜 142的氮浓度高于6×1021原子/ cc。 因此，第二氮化硅膜142增加了从玻璃基板20进入的移动离子的阻挡效应，使得移动离子不太可能存储在与沟道层50的界面中。第一氮化硅膜141增加了介质击穿 栅极绝缘膜140的电压。

公开(公告)号：US20120193633A1

公开(公告)日：2012-08-02

申请号：US13499846

申请日：2010-09-21

申请人： Akihiko Kohno ,  Toshio Mizuki ,  Kohichi Tanaka

发明人： Akihiko Kohno ,  Toshio Mizuki ,  Kohichi Tanaka

IPC分类号： H01L29/38 ,  H01L21/205

CPC分类号： H01J37/32192 ,  C23C16/24 ,  C23C16/4401 ,  C23C16/511 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L29/04 ,  H01L29/66765

摘要： A method for fabricating a semiconductor device according to the present invention includes the steps of: (a) providing a substrate (11a) in a chamber (26); (b) supplying a microwave into the chamber (26) through a dielectric plate (24), of which one surface that faces the chamber is made of alumina, thereby depositing a microcrystalline silicon film (14) with an aluminum concentration of 1.0×1016 atoms/cm3 or less on the substrate (11a) by high-density plasma CVD process; and (c) making a thin-film transistor that uses the microcrystalline silicon film as its active layer. As a result, a semiconductor device including a TFT that uses a microcrystalline silicon film with a mobility of more than 0.5 cm2/Vs as its active layer is obtained.

摘要翻译： 根据本发明的制造半导体器件的方法包括以下步骤：（a）在腔室（26）中提供衬底（11a）; （b）通过电介质板（24）将微波提供到腔室（26）中，其中面向腔室的一个表面由氧化铝制成，从而沉积铝浓度为1.0×1016的微晶硅膜（14） 原子/ cm 3以下通过高密度等离子体CVD工艺在基板（11a）上; 和（c）制造使用微晶硅膜作为有源层的薄膜晶体管。 结果，获得包括使用迁移率大于0.5cm2 / Vs的微晶硅膜作为有源层的TFT的半导体器件。

公开(公告)号：US08717340B2

公开(公告)日：2014-05-06

申请号：US13519562

申请日：2010-10-20

申请人： Toshio Mizuki ,  Akihiko Kohno ,  Kohichi Tanaka

发明人： Toshio Mizuki ,  Akihiko Kohno ,  Kohichi Tanaka

IPC分类号： G09G5/00

CPC分类号： H01L29/78678 ,  G02F1/1368 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66765

摘要： Disclosed is a thin film transistor that is provided with a gate insulating film that is inexpensive, and that is less likely to have a low-density microcrystalline silicon layer formed thereon due to plasma induced damage, while suppressing fluctuation of a threshold voltage. In a TFT (100) having the bottom gate structure, since a silicon nitride film (31) having a natural oxide film (32) formed on the surface thereof is used as the gate insulating film (30), the gate insulating film (30) is not only capable of preventing the alkali metal ions contained in a glass substrate (10) from entering the gate insulating film (30), but also capable of suppressing a formation of the low-density microcrystalline silicon layer on the surface of a microcrystalline silicon film (41) on the side in contact with the gate insulating film (30). Since the mobility of the microcrystalline silicon film (41) is increased, the operation speed of the TFT (100) can be improved. Thus, with the simpler configuration, the TFT (100) having the same electrical characteristics as those of the conventional TFTs can be provided.

摘要翻译： 公开了一种薄膜晶体管，其具有便宜的栅极绝缘膜，并且由于等离子体引起的损伤而不太可能具有形成在其上的低密度微晶硅层，同时抑制阈值电压的波动。 在具有底栅结构的TFT（100）中，由于使用在其表面上形成有自然氧化膜（32）的氮化硅膜（31）作为栅极绝缘膜（30），所以栅极绝缘膜 ）不仅能够防止玻璃基板（10）中所含的碱金属离子进入栅极绝缘膜（30），而且能够抑制微晶硅表面上的低密度微晶硅层的形成 在与栅极绝缘膜（30）接触的一侧的硅膜（41）。 由于微晶硅膜（41）的迁移率增加，所以可以提高TFT（100）的工作速度。 因此，通过简单的结构，可以提供具有与常规TFT相同的电特性的TFT（100）。

公开(公告)号：US20130087802A1

公开(公告)日：2013-04-11

申请号：US13805412

申请日：2011-03-25

申请人： Akihiko Kohno ,  Toshio Mizuki ,  Kohichi Tanaka

发明人： Akihiko Kohno ,  Toshio Mizuki ,  Kohichi Tanaka

IPC分类号： H01L29/786 ,  H01L29/66

CPC分类号： H01L29/786 ,  H01L27/1214 ,  H01L29/66765 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78678 ,  H01L29/78696

摘要： It is an object to increase the mobility of a thin film transistor having an active layer including a microcrystalline semiconductor film. Upon fabricating an inverted staggered type TFT 10, a substrate is vacuum-transferred to a plasma enhanced CVD apparatus such that a surface of a microcrystalline silicon film (active layer 40) exposed by gap etching is not exposed to the air. An insulating film 80 is deposited by the plasma enhanced CVD apparatus so as to completely cover the exposed surface of the microcrystalline silicon film. By this, even if the microcrystalline silicon film is exposed to the air, oxygen cannot be adsorbed on the surface thereof and thus diffusion of oxygen into the microcrystalline silicon film can be suppressed. In addition, since N+ silicon films composing contact layers 50a and 50b directly contact with the microcrystalline silicon film, the contact resistance can be reduced. In this manner, the mobility of the TFT 10 having the active layer 40 including the microcrystalline silicon film can be increased.

摘要翻译： 本发明的目的是增加具有包括微晶半导体膜的有源层的薄膜晶体管的迁移率。 在制造反向交错型TFT10时，将基板真空转印到等离子体增强CVD装置中，使得通过间隙蚀刻而暴露的微晶硅膜（有源层40）的表面不暴露于空气。 通过等离子体增强CVD装置沉积绝缘膜80，以完全覆盖微晶硅膜的暴露表面。 由此，即使微晶硅膜暴露于空气中，也不能在其表面吸附氧，因此可以抑制氧向微晶硅膜的扩散。 此外，由于构成接触层50a和50b的N +硅膜与微晶硅膜直接接触，所以可以降低接触电阻。 以这种方式，可以增加具有包括微晶硅膜的有源层40的TFT 10的迁移率。

公开(公告)号：US20120287094A1

公开(公告)日：2012-11-15

申请号：US13519562

申请日：2010-10-20

申请人： Toshio Mizuki ,  Akihiko Kohno ,  Kohichi Tanaka

发明人： Toshio Mizuki ,  Akihiko Kohno ,  Kohichi Tanaka

IPC分类号： G09G5/00 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L29/78678 ,  G02F1/1368 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66765

摘要： Disclosed is a thin film transistor that is provided with a gate insulating film that is inexpensive, and that is less likely to have a low-density microcrystalline silicon layer formed thereon due to plasma induced damage, while suppressing fluctuation of a threshold voltage. In a TFT (100) having the bottom gate structure, since a silicon nitride film (31) having a natural oxide film (32) formed on the surface thereof is used as the gate insulating film (30), the gate insulating film (30) is not only capable of preventing the alkali metal ions contained in a glass substrate (10) from entering the gate insulating film (30), but also capable of suppressing a formation of the low-density microcrystalline silicon layer on the surface of a microcrystalline silicon film (41) on the side in contact with the gate insulating film (30). Since the mobility of the microcrystalline silicon film (41) is increased, the operation speed of the TFT (100) can be improved. Thus, with the simpler configuration, the TFT (100) having the same electrical characteristics as those of the conventional TFTs can be provided.

摘要翻译： 公开了一种薄膜晶体管，其具有便宜的栅极绝缘膜，并且由于等离子体引起的损伤而不太可能具有形成在其上的低密度微晶硅层，同时抑制阈值电压的波动。 在具有底栅结构的TFT（100）中，由于使用在其表面上形成有自然氧化膜（32）的氮化硅膜（31）作为栅极绝缘膜（30），所以栅极绝缘膜 ）不仅能够防止玻璃基板（10）中所含的碱金属离子进入栅极绝缘膜（30），而且能够抑制微晶硅表面上的低密度微晶硅层的形成 在与栅极绝缘膜（30）接触的一侧的硅膜（41）。 由于微晶硅膜（41）的迁移率增加，所以可以提高TFT（100）的工作速度。 因此，通过简单的结构，可以提供具有与常规TFT相同的电特性的TFT（100）。

公开(公告)号：US20120216828A1

公开(公告)日：2012-08-30

申请号：US13504242

申请日：2010-05-17

申请人： Junichi Tanaka ,  Akihiko Kohno

发明人： Junichi Tanaka ,  Akihiko Kohno

IPC分类号： B08B3/08 ,  B08B7/04 ,  B08B3/02

CPC分类号： B08B3/022 ,  B08B2203/005 ,  G03F7/423 ,  H01L21/67051 ,  H01L27/1259

摘要： Disclosed is a substrate cleaning device provided with: a generation unit that generates ozone micro-nanobubble water; a nozzle header unit provided with a plurality of spray nozzles that spray the ozone micro-nanobubble water; and a substrate support unit that supports a substrate to be treated. The surface of the substrate supported by the substrate support unit is cleaned by spraying the ozone micro-nanobubble water from the plurality of spray nozzles onto the substrate.

摘要翻译： 本发明公开了一种基板清洗装置，具备：生成臭氧微纳米水的发生单元; 设置有喷射臭氧微纳米水的多个喷嘴的喷嘴头单元; 以及支撑待处理基板的基板支撑单元。 由基板支撑单元支撑的基板的表面通过将多个喷嘴中的臭氧微纳米泡沫水喷射到基板上而被清洁。